1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI controller
8
9maintainers:
10  - Krishna Manikandan <[email protected]>
11
12properties:
13  compatible:
14    oneOf:
15      - items:
16          - enum:
17              - qcom,apq8064-dsi-ctrl
18              - qcom,msm8226-dsi-ctrl
19              - qcom,msm8916-dsi-ctrl
20              - qcom,msm8953-dsi-ctrl
21              - qcom,msm8974-dsi-ctrl
22              - qcom,msm8976-dsi-ctrl
23              - qcom,msm8996-dsi-ctrl
24              - qcom,msm8998-dsi-ctrl
25              - qcom,qcm2290-dsi-ctrl
26              - qcom,sc7180-dsi-ctrl
27              - qcom,sc7280-dsi-ctrl
28              - qcom,sdm660-dsi-ctrl
29              - qcom,sdm670-dsi-ctrl
30              - qcom,sdm845-dsi-ctrl
31              - qcom,sm6115-dsi-ctrl
32              - qcom,sm6125-dsi-ctrl
33              - qcom,sm6150-dsi-ctrl
34              - qcom,sm6350-dsi-ctrl
35              - qcom,sm6375-dsi-ctrl
36              - qcom,sm7150-dsi-ctrl
37              - qcom,sm8150-dsi-ctrl
38              - qcom,sm8250-dsi-ctrl
39              - qcom,sm8350-dsi-ctrl
40              - qcom,sm8450-dsi-ctrl
41              - qcom,sm8550-dsi-ctrl
42              - qcom,sm8650-dsi-ctrl
43          - const: qcom,mdss-dsi-ctrl
44      - enum:
45          - qcom,dsi-ctrl-6g-qcm2290
46          - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
47        deprecated: true
48
49  reg:
50    maxItems: 1
51
52  reg-names:
53    const: dsi_ctrl
54
55  interrupts:
56    maxItems: 1
57
58  clocks:
59    description: |
60      Several clocks are used, depending on the variant. Typical ones are::
61       - bus:: Display AHB clock.
62       - byte:: Display byte clock.
63       - byte_intf:: Display byte interface clock.
64       - core:: Display core clock.
65       - core_mss:: Core MultiMedia SubSystem clock.
66       - iface:: Display AXI clock.
67       - mdp_core:: MDP Core clock.
68       - mnoc:: MNOC clock
69       - pixel:: Display pixel clock.
70    minItems: 3
71    maxItems: 9
72
73  clock-names:
74    minItems: 3
75    maxItems: 9
76
77  phys:
78    maxItems: 1
79
80  phy-names:
81    deprecated: true
82    const: dsi
83
84  syscon-sfpb:
85    description: A phandle to mmss_sfpb syscon node (only for DSIv2).
86    $ref: /schemas/types.yaml#/definitions/phandle
87
88  qcom,dual-dsi-mode:
89    type: boolean
90    description: |
91      Indicates if the DSI controller is driving a panel which needs
92      2 DSI links.
93
94  qcom,master-dsi:
95    type: boolean
96    description: |
97      Indicates if the DSI controller is the master DSI controller when
98      qcom,dual-dsi-mode enabled.
99
100  qcom,sync-dual-dsi:
101    type: boolean
102    description: |
103      Indicates if the DSI controller needs to sync the other DSI controller
104      with MIPI DCS commands when qcom,dual-dsi-mode enabled.
105
106  assigned-clocks:
107    minItems: 2
108    maxItems: 4
109    description: |
110      Parents of "byte" and "pixel" for the given platform.
111      For DSIv2 platforms this should contain "byte", "esc", "src" and
112      "pixel_src" clocks.
113
114  assigned-clock-parents:
115    minItems: 2
116    maxItems: 4
117    description: |
118      The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
119
120  power-domains:
121    maxItems: 1
122
123  operating-points-v2: true
124
125  opp-table:
126    type: object
127
128  ports:
129    $ref: /schemas/graph.yaml#/properties/ports
130    description: |
131      Contains DSI controller input and output ports as children, each
132      containing one endpoint subnode.
133
134    properties:
135      port@0:
136        $ref: /schemas/graph.yaml#/$defs/port-base
137        unevaluatedProperties: false
138        description: |
139          Input endpoints of the controller.
140        properties:
141          endpoint:
142            $ref: /schemas/media/video-interfaces.yaml#
143            unevaluatedProperties: false
144            properties:
145              data-lanes:
146                maxItems: 4
147                minItems: 1
148                items:
149                  enum: [ 0, 1, 2, 3 ]
150
151      port@1:
152        $ref: /schemas/graph.yaml#/$defs/port-base
153        unevaluatedProperties: false
154        description: |
155          Output endpoints of the controller.
156        properties:
157          endpoint:
158            $ref: /schemas/media/video-interfaces.yaml#
159            unevaluatedProperties: false
160            properties:
161              data-lanes:
162                maxItems: 4
163                minItems: 1
164                items:
165                  enum: [ 0, 1, 2, 3 ]
166
167              qcom,te-source:
168                $ref: /schemas/types.yaml#/definitions/string
169                description:
170                  Specifies the source of vsync signal from the panel used for
171                  tearing elimination.
172                default: mdp_vsync_p
173                enum:
174                  - mdp_vsync_p
175                  - mdp_vsync_s
176                  - mdp_vsync_e
177                  - timer0
178                  - timer1
179                  - timer2
180                  - timer3
181                  - timer4
182
183    required:
184      - port@0
185      - port@1
186
187  avdd-supply:
188    description:
189      Phandle to vdd regulator device node
190
191  refgen-supply:
192    description:
193      Phandle to REFGEN regulator device node
194
195  vcca-supply:
196    description:
197      Phandle to vdd regulator device node
198
199  vdd-supply:
200    description:
201      VDD regulator
202
203  vddio-supply:
204    description:
205      VDD-IO regulator
206
207  vdda-supply:
208    description:
209      VDDA regulator
210
211required:
212  - compatible
213  - reg
214  - reg-names
215  - interrupts
216  - clocks
217  - clock-names
218  - phys
219  - assigned-clocks
220  - assigned-clock-parents
221  - ports
222
223allOf:
224  - $ref: ../dsi-controller.yaml#
225  - if:
226      properties:
227        compatible:
228          contains:
229            enum:
230              - qcom,apq8064-dsi-ctrl
231    then:
232      properties:
233        clocks:
234          maxItems: 7
235        clock-names:
236          items:
237            - const: iface
238            - const: bus
239            - const: core_mmss
240            - const: src
241            - const: byte
242            - const: pixel
243            - const: core
244
245  - if:
246      properties:
247        compatible:
248          contains:
249            enum:
250              - qcom,msm8916-dsi-ctrl
251    then:
252      properties:
253        clocks:
254          maxItems: 6
255        clock-names:
256          items:
257            - const: mdp_core
258            - const: iface
259            - const: bus
260            - const: byte
261            - const: pixel
262            - const: core
263
264  - if:
265      properties:
266        compatible:
267          contains:
268            enum:
269              - qcom,msm8953-dsi-ctrl
270              - qcom,msm8976-dsi-ctrl
271    then:
272      properties:
273        clocks:
274          maxItems: 6
275        clock-names:
276          items:
277            - const: mdp_core
278            - const: iface
279            - const: bus
280            - const: byte
281            - const: pixel
282            - const: core
283
284  - if:
285      properties:
286        compatible:
287          contains:
288            enum:
289              - qcom,msm8226-dsi-ctrl
290              - qcom,msm8974-dsi-ctrl
291    then:
292      properties:
293        clocks:
294          maxItems: 7
295        clock-names:
296          items:
297            - const: mdp_core
298            - const: iface
299            - const: bus
300            - const: byte
301            - const: pixel
302            - const: core
303            - const: core_mmss
304
305  - if:
306      properties:
307        compatible:
308          contains:
309            enum:
310              - qcom,msm8996-dsi-ctrl
311    then:
312      properties:
313        clocks:
314          maxItems: 7
315        clock-names:
316          items:
317            - const: mdp_core
318            - const: byte
319            - const: iface
320            - const: bus
321            - const: core_mmss
322            - const: pixel
323            - const: core
324
325  - if:
326      properties:
327        compatible:
328          contains:
329            enum:
330              - qcom,msm8998-dsi-ctrl
331              - qcom,sm6125-dsi-ctrl
332              - qcom,sm6350-dsi-ctrl
333    then:
334      properties:
335        clocks:
336          maxItems: 6
337        clock-names:
338          items:
339            - const: byte
340            - const: byte_intf
341            - const: pixel
342            - const: core
343            - const: iface
344            - const: bus
345
346  - if:
347      properties:
348        compatible:
349          contains:
350            enum:
351              - qcom,sc7180-dsi-ctrl
352              - qcom,sc7280-dsi-ctrl
353              - qcom,sm6150-dsi-ctrl
354              - qcom,sm7150-dsi-ctrl
355              - qcom,sm8150-dsi-ctrl
356              - qcom,sm8250-dsi-ctrl
357              - qcom,sm8350-dsi-ctrl
358              - qcom,sm8450-dsi-ctrl
359              - qcom,sm8550-dsi-ctrl
360              - qcom,sm8650-dsi-ctrl
361    then:
362      properties:
363        clocks:
364          maxItems: 6
365        clock-names:
366          items:
367            - const: byte
368            - const: byte_intf
369            - const: pixel
370            - const: core
371            - const: iface
372            - const: bus
373
374  - if:
375      properties:
376        compatible:
377          contains:
378            enum:
379              - qcom,sdm660-dsi-ctrl
380    then:
381      properties:
382        clocks:
383          maxItems: 9
384        clock-names:
385          items:
386            - const: mdp_core
387            - const: byte
388            - const: byte_intf
389            - const: mnoc
390            - const: iface
391            - const: bus
392            - const: core_mmss
393            - const: pixel
394            - const: core
395
396  - if:
397      properties:
398        compatible:
399          contains:
400            enum:
401              - qcom,sdm845-dsi-ctrl
402              - qcom,sm6115-dsi-ctrl
403              - qcom,sm6375-dsi-ctrl
404    then:
405      properties:
406        clocks:
407          maxItems: 6
408        clock-names:
409          items:
410            - const: byte
411            - const: byte_intf
412            - const: pixel
413            - const: core
414            - const: iface
415            - const: bus
416
417unevaluatedProperties: false
418
419examples:
420  - |
421    #include <dt-bindings/interrupt-controller/arm-gic.h>
422    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
423    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
424    #include <dt-bindings/power/qcom-rpmpd.h>
425
426    dsi@ae94000 {
427        compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
428        reg = <0x0ae94000 0x400>;
429        reg-names = "dsi_ctrl";
430
431        #address-cells = <1>;
432        #size-cells = <0>;
433
434        interrupt-parent = <&mdss>;
435        interrupts = <4>;
436
437        clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
438                 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
439                 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
440                 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
441                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
442                 <&dispcc DISP_CC_MDSS_AXI_CLK>;
443        clock-names = "byte",
444                      "byte_intf",
445                      "pixel",
446                      "core",
447                      "iface",
448                      "bus";
449
450        phys = <&dsi0_phy>;
451        phy-names = "dsi";
452
453        assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
454        assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
455
456        power-domains = <&rpmhpd SC7180_CX>;
457        operating-points-v2 = <&dsi_opp_table>;
458
459        ports {
460            #address-cells = <1>;
461            #size-cells = <0>;
462
463            port@0 {
464                reg = <0>;
465                endpoint {
466                    remote-endpoint = <&dpu_intf1_out>;
467                };
468            };
469
470            port@1 {
471                reg = <1>;
472                endpoint {
473                    remote-endpoint = <&sn65dsi86_in>;
474                    data-lanes = <0 1 2 3>;
475                    qcom,te-source = "mdp_vsync_e";
476                };
477            };
478        };
479    };
480...
481