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/XiangShan/src/main/scala/xiangshan/mem/
H A DMemBlock.scala418 val vsMergeBuffer = Seq.fill(VstuCnt)(Module(new VSMergeBufferImp)) constant
1550 vsMergeBuffer(i).io.fromPipeline := DontCare
1551 vsMergeBuffer(i).io.fromSplit := DontCare
1553vsMergeBuffer(i).io.fromMisalignBuffer.get.flush := storeMisalignBuffer.io.toVecStoreMergeBuffer(i…
1554vsMergeBuffer(i).io.fromMisalignBuffer.get.mbIndex := storeMisalignBuffer.io.toVecStoreMergeBuffer…
1562 vsSplit(i).io.toMergeBuffer <> vsMergeBuffer(i).io.fromSplit.head
1613 storeMisalignBuffer.io.vecWriteBack(i).ready := vsMergeBuffer(i).io.fromPipeline.head.ready
1616 vsMergeBuffer(i).io.fromPipeline.head.valid := storeUnits(i).io.vecstout.valid
1617 vsMergeBuffer(i).io.fromPipeline.head.bits := storeUnits(i).io.vecstout.bits
1619vsMergeBuffer(i).io.fromPipeline.head.valid := storeMisalignBuffer.io.vecWriteBack(i).valid
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