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Searched refs:__ASM (Results 1 – 25 of 62) sorted by relevance

123

/btstack/port/samv71-xplained-atwilc3000/ASF/thirdparty/CMSIS/Include/
H A Dcore_cmFunc.h66 register uint32_t __regControl __ASM("control"); in __get_CONTROL()
79 register uint32_t __regControl __ASM("control"); in __set_CONTROL()
92 register uint32_t __regIPSR __ASM("ipsr"); in __get_IPSR()
105 register uint32_t __regAPSR __ASM("apsr"); in __get_APSR()
118 register uint32_t __regXPSR __ASM("xpsr"); in __get_xPSR()
131 register uint32_t __regProcessStackPointer __ASM("psp"); in __get_PSP()
144 register uint32_t __regProcessStackPointer __ASM("psp"); in __set_PSP()
157 register uint32_t __regMainStackPointer __ASM("msp"); in __get_MSP()
170 register uint32_t __regMainStackPointer __ASM("msp"); in __set_MSP()
183 register uint32_t __regPriMask __ASM("primask"); in __get_PRIMASK()
[all …]
H A Dcore_cmSimd.h139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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H A Dcore_cmInstr.h129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) in __REV16()
144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) in __REVSH()
300 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) in __RRX()
390 __ASM volatile ("nop"); in __NOP()
401 __ASM volatile ("wfi"); in __WFI()
412 __ASM volatile ("wfe"); in __WFE()
422 __ASM volatile ("sev"); in __SEV()
434 __ASM volatile ("isb"); in __ISB()
445 __ASM volatile ("dsb"); in __DSB()
456 __ASM volatile ("dmb"); in __DMB()
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/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/arm/CMSIS_5/CMSIS/Core/Include/
H A Dcmsis_gcc.h40 #ifndef __ASM
41 #define __ASM __asm macro
117 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
228 #define __NOP() __ASM volatile ("nop")
234 #define __WFI() __ASM volatile ("wfi":::"memory")
242 #define __WFE() __ASM volatile ("wfe":::"memory")
249 #define __SEV() __ASM volatile ("sev")
260 __ASM volatile ("isb 0xF":::"memory"); in __ISB()
271 __ASM volatile ("dsb 0xF":::"memory"); in __DSB()
282 __ASM volatile ("dmb 0xF":::"memory"); in __DMB()
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H A Dcmsis_armclang_ltm.h33 #ifndef __ASM
34 #define __ASM __asm macro
110 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
276 #define __BKPT(value) __ASM volatile ("bkpt "#value)
423 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); in __RRX()
438 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRBT()
453 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRHT()
468 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRT()
481 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRBT()
493 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRHT()
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H A Dcmsis_armclang.h33 #ifndef __ASM
34 #define __ASM __asm macro
110 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
278 #define __BKPT(value) __ASM volatile ("bkpt "#value)
429 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); in __RRX()
444 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRBT()
459 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRHT()
474 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRT()
487 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRBT()
499 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRHT()
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/btstack/port/stm32-l073rz-nucleo-em9304/Drivers/CMSIS/Include/
H A Dcmsis_armcc_V6.h52 __ASM volatile ("cpsie i" : : : "memory"); in __enable_irq()
63 __ASM volatile ("cpsid i" : : : "memory"); in __disable_irq()
76 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
91 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
104 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
116 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
130 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
145 __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); in __TZ_get_IPSR_NS()
160 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
175 __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); in __TZ_get_APSR_NS()
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H A Dcmsis_gcc.h60 __ASM volatile ("cpsie i" : : : "memory"); in __enable_irq()
71 __ASM volatile ("cpsid i" : : : "memory"); in __disable_irq()
84 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
96 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
109 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
123 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
138 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); in __get_xPSR()
152 __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); in __get_PSP()
164 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); in __set_PSP()
177 __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); in __get_MSP()
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/btstack/port/stm32-l476rg-nucleo-sx1280/Drivers/CMSIS/Include/
H A Dcmsis_gcc.h40 #ifndef __ASM
41 #define __ASM __asm macro
117 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
198 __ASM volatile ("cpsie i" : : : "memory"); in __enable_irq()
209 __ASM volatile ("cpsid i" : : : "memory"); in __disable_irq()
222 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
237 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
250 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
262 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
276 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
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H A Dcmsis_armclang.h37 #ifndef __ASM
38 #define __ASM __asm macro
114 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
170 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
185 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
198 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
210 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
224 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
238 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
252 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); in __get_xPSR()
[all …]
/btstack/port/stm32-l451-miromico-sx1280/Drivers/CMSIS/Include/
H A Dcmsis_gcc.h40 #ifndef __ASM
41 #define __ASM __asm macro
131 __ASM volatile ("cpsie i" : : : "memory"); in __enable_irq()
142 __ASM volatile ("cpsid i" : : : "memory"); in __disable_irq()
155 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
170 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
183 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
195 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
209 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
223 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
[all …]
H A Dcmsis_armclang.h37 #ifndef __ASM
38 #define __ASM __asm macro
146 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
161 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
174 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
186 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
200 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
214 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
228 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); in __get_xPSR()
242 __ASM volatile ("MRS %0, psp" : "=r" (result) ); in __get_PSP()
[all …]
/btstack/port/stm32-wb55xx-nucleo-freertos/Drivers/CMSIS/Include/
H A Dcmsis_gcc.h40 #ifndef __ASM
41 #define __ASM __asm macro
131 __ASM volatile ("cpsie i" : : : "memory"); in __enable_irq()
142 __ASM volatile ("cpsid i" : : : "memory"); in __disable_irq()
155 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
170 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
183 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
195 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
209 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
223 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
[all …]
/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Include/
H A Dcmsis_gcc.h40 #ifndef __ASM
41 #define __ASM __asm macro
131 __ASM volatile ("cpsie i" : : : "memory"); in __enable_irq()
142 __ASM volatile ("cpsid i" : : : "memory"); in __disable_irq()
155 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
170 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
183 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
195 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
209 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
223 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
[all …]
H A Dcmsis_armclang.h37 #ifndef __ASM
38 #define __ASM __asm macro
146 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
161 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
174 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
186 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
200 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
214 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
228 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); in __get_xPSR()
242 __ASM volatile ("MRS %0, psp" : "=r" (result) ); in __get_PSP()
[all …]
/btstack/port/stm32-f4discovery-cc256x/Drivers/CMSIS/Include/
H A Dcmsis_gcc.h40 #ifndef __ASM
41 #define __ASM __asm macro
131 __ASM volatile ("cpsie i" : : : "memory"); in __enable_irq()
142 __ASM volatile ("cpsid i" : : : "memory"); in __disable_irq()
155 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
170 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
183 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
195 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
209 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
223 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
[all …]
H A Dcmsis_armclang.h37 #ifndef __ASM
38 #define __ASM __asm macro
146 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
161 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
174 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
186 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
200 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
214 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
228 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); in __get_xPSR()
242 __ASM volatile ("MRS %0, psp" : "=r" (result) ); in __get_PSP()
[all …]
/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Core/Include/
H A Dcmsis_gcc.h40 #ifndef __ASM
41 #define __ASM __asm macro
131 __ASM volatile ("cpsie i" : : : "memory"); in __enable_irq()
142 __ASM volatile ("cpsid i" : : : "memory"); in __disable_irq()
155 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
170 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
183 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
195 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
209 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
223 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
[all …]
H A Dcmsis_armclang.h37 #ifndef __ASM
38 #define __ASM __asm macro
146 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
161 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
174 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
186 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
200 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
214 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
228 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); in __get_xPSR()
242 __ASM volatile ("MRS %0, psp" : "=r" (result) ); in __get_PSP()
[all …]
/btstack/port/msp432p401lp-cc256x/CMSIS/
H A Dcmsis_gcc.h52 __ASM volatile ("cpsie i" : : : "memory"); in __enable_irq()
63 __ASM volatile ("cpsid i" : : : "memory"); in __disable_irq()
77 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
90 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
104 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
119 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
134 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); in __get_xPSR()
149 __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); in __get_PSP()
162 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); in __set_PSP()
176 __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); in __get_MSP()
[all …]
H A Dcore_cm4_simd.h162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
[all …]
/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy/ssp/inc/bsp/cmsis/Include/
H A Dcmsis_gcc.h40 #ifndef __ASM
41 #define __ASM __asm macro
128 __ASM volatile ("cpsie i" : : : "memory"); in __enable_irq()
139 __ASM volatile ("cpsid i" : : : "memory"); in __disable_irq()
152 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
167 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
180 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
192 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
206 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
220 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
[all …]
H A Dcmsis_armclang.h35 #ifndef __ASM
36 #define __ASM __asm macro
141 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
156 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); in __TZ_get_CONTROL_NS()
169 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
181 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); in __TZ_set_CONTROL_NS()
195 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
209 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
223 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); in __get_xPSR()
237 __ASM volatile ("MRS %0, psp" : "=r" (result) ); in __get_PSP()
[all …]
/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Core_A/Include/
H A Dcmsis_gcc.h40 #ifndef __ASM
41 #define __ASM asm macro
112 #define __NOP() __ASM volatile ("nop")
117 #define __WFI() __ASM volatile ("wfi")
122 #define __WFE() __ASM volatile ("wfe")
127 #define __SEV() __ASM volatile ("sev")
137 __ASM volatile ("isb 0xF":::"memory"); in __ISB()
148 __ASM volatile ("dsb 0xF":::"memory"); in __DSB()
158 __ASM volatile ("dmb 0xF":::"memory"); in __DMB()
174 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); in __REV()
[all …]
H A Dcmsis_armclang.h35 #ifndef __ASM
36 #define __ASM __asm macro
203 #define __BKPT(value) __ASM volatile ("bkpt "#value)
321 __ASM volatile("MRS %0, cpsr" : "=r" (result) ); in __get_CPSR()
330 __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); in __set_CPSR()
346 __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); in __set_mode()
355 __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); in __get_SP()
364 __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); in __set_SP()
374 __ASM volatile( in __get_SP_usr()
390 __ASM volatile( in __set_SP_usr()
[all …]

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