/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy/ssp/src/driver/r_cgc/ |
H A D | r_cgc.c | 85 static ssp_err_t r_cgc_stabilization_wait(cgc_clock_t clock); 88 static ssp_err_t r_cgc_check_peripheral_clocks(cgc_system_clocks_t clock); 106 static void r_cgc_clock_start (R_SYSTEM_Type * p_system_reg, cgc_clock_t clock); 107 static void r_cgc_clock_stop (R_SYSTEM_Type * p_system_reg, cgc_clock_t clock); 108 static bool r_cgc_clock_check (R_SYSTEM_Type * p_system_reg, cgc_clock_t clock); 110 static void r_cgc_clock_wait_set (R_SYSTEM_Type * p_system_reg, cgc_clock_t clock, uint8_t time); 111 static void r_cgc_clock_source_set (R_SYSTEM_Type * p_system_reg, cgc_clock_t clock); 113 static uint32_t r_cgc_clock_divider_get (R_SYSTEM_Type * p_system_reg, cgc_system_clocks_t clock); 114 static uint32_t r_cgc_clock_hzget (R_SYSTEM_Type * p_system_reg, cgc_system_clocks_t clock); 119 static void r_cgc_clockout_cfg (R_SYSTEM_Type * p_system_reg, cgc_clock_t clock, cgc_clockout_divid… [all …]
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H A D | r_cgc_private_api.h | 35 ssp_err_t R_CGC_SystemClockFreqGet (cgc_system_clocks_t clock, uint32_t * freq_hz); 42 ssp_err_t R_CGC_ClockOutCfg (cgc_clock_t clock, cgc_clockout_dividers_t divider); 45 ssp_err_t R_CGC_LCDClockCfg (cgc_clock_t clock); 48 ssp_err_t R_CGC_SDADCClockCfg (cgc_clock_t clock);
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H A D | r_cgc_private.h | 67 bool r_cgc_clock_run_state_get (R_SYSTEM_Type * p_system_reg, cgc_clock_t clock);
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/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy/ssp/src/bsp/mcu/s1ja/ |
H A D | bsp_clocks.c | 78 cgc_clock_t clock; in bsp_clock_init() local 85 clock = BSP_CFG_CLOCK_SOURCE; in bsp_clock_init() 86 err = g_cgc_on_cgc.clockStart(clock, NULL); in bsp_clock_init() 95 if ((CGC_CLOCK_MOCO != clock) && (CGC_CLOCK_LOCO != clock) && (CGC_CLOCK_SUBCLOCK != clock)) in bsp_clock_init() 97 while (SSP_ERR_STABILIZED != g_cgc_on_cgc.clockCheck(clock)) in bsp_clock_init() 109 err = g_cgc_on_cgc.systemClockSet(clock, &sys_cfg); in bsp_clock_init()
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H A D | bsp_feature.c | 89 p_sci_feature->clock = (uint8_t) CGC_SYSTEM_CLOCKS_PCLKB; in R_BSP_FeatureSciGet() 94 p_rspi_feature->clock = (uint8_t) CGC_SYSTEM_CLOCKS_PCLKB; in R_BSP_FeatureRspiGet() 135 p_can_feature->clock = CGC_SYSTEM_CLOCKS_ICLK; in R_BSP_FeatureCanGet()
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/btstack/port/samv71-xplained-atwilc3000/ASF/common/services/clock/samv71/ |
H A D | osc.h | 66 # warning The board slow clock xtal frequency has not been defined. 71 # warning The board slow clock bypass frequency has not been defined. 76 # warning The board main clock xtal frequency has not been defined. 81 # warning The board main clock bypass frequency has not been defined. 86 # warning The board main clock xtal startup time has not been defined.
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/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy/ssp/src/driver/r_cgc/hw/ |
H A D | hw_cgc.h | 183 __STATIC_INLINE void HW_CGC_LCDClockCfg (R_SYSTEM_Type * p_system_reg, uint8_t clock) in HW_CGC_LCDClockCfg() argument 185 p_system_reg->SLCDSCKCR_b.LCDSCKSEL = clock & 0xFU; in HW_CGC_LCDClockCfg() 248 __STATIC_INLINE void HW_CGC_SDADCClockCfg (R_SYSTEM_Type * p_system_reg, uint8_t clock) in HW_CGC_SDADCClockCfg() argument 250 if (clock == CGC_CLOCK_HOCO) in HW_CGC_SDADCClockCfg() 358 __STATIC_INLINE bool HW_CGC_ClockSourceValidCheck (cgc_clock_t clock) in HW_CGC_ClockSourceValidCheck() argument 360 return (clock < CGC_CLOCK_NUM_CLOCKS); in HW_CGC_ClockSourceValidCheck()
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/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy/ssp/inc/driver/api/ |
H A D | r_cgc_api.h | 275 ssp_err_t (* systemClockFreqGet)(cgc_system_clocks_t clock, uint32_t * p_freq_hz); 326 ssp_err_t (* clockOutCfg)(cgc_clock_t clock, cgc_clockout_dividers_t divider); 345 ssp_err_t (* lcdClockCfg)(cgc_clock_t clock); 364 ssp_err_t (* sdadcClockCfg)(cgc_clock_t clock);
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/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy/ssp/src/bsp/mcu/all/ |
H A D | bsp_feature.h | 52 uint8_t clock; ///< Which clock the SCI is connected to member 58 uint8_t clock; ///< Which clock the RSPI is connected to member 101 uint8_t clock; ///< Which clock to compare PCLKB to member
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/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/fsp/src/bsp/mcu/all/ |
H A D | bsp_common.h | 248 uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock); 276 __STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) in R_FSP_SystemClockHzGet() argument 280 uint32_t clock_div = (sckdivcr >> clock) & FSP_PRIV_SCKDIVCR_DIV_MASK; in R_FSP_SystemClockHzGet()
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H A D | bsp_clocks.c | 695 void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr) in bsp_prv_clock_set() argument 708 uint32_t clock_freq_hz_post_change = g_clock_freq[clock] >> iclk_div; in bsp_prv_clock_set() 723 R_SYSTEM->SCKSCR = (uint8_t) clock; in bsp_prv_clock_set() 730 R_SYSTEM->SCKSCR = (uint8_t) clock; in bsp_prv_clock_set() 1609 uint32_t R_BSP_SourceClockHzGet (fsp_priv_source_clock_t clock) in R_BSP_SourceClockHzGet() argument 1611 uint32_t source_clock = g_clock_freq[clock]; in R_BSP_SourceClockHzGet()
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H A D | bsp_clocks.h | 349 void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr);
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/btstack/doc/manual/docs-template/ |
H A D | porting.md | 11 system clock with millisecond resolution. BTstack’s timing requirements 19 If your platform doesn’t require a system clock or if you already have a 45 If your platform already has a system clock or it is more convenient to 46 provide such a clock, you can use the Time MS Hardware Abstraction in
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/btstack/port/samv71-xplained-atwilc3000/example/template/ |
H A D | config.mk | 60 common/services/clock/samv71/sysclk.c \ 85 common/services/clock \
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/btstack/port/max32630-fthr/scripts/ |
H A D | max3263x_hdk.cfg | 24 # max32630 clock speed 96 (MHz)
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/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/fsp/inc/instances/ |
H A D | r_sci_uart.h | 183 …sci_clk_src_t clock; ///< The source clock for the baud-rate generator.… member
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/btstack/port/samv71-xplained-atwilc3000/ASF/sam/drivers/usart/ |
H A D | usart.c | 535 uint32_t clock, uint32_t ul_mck) in usart_set_iso7816_clock() argument 540 cd = (ul_mck + clock / 2) / clock; in usart_set_iso7816_clock()
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/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/fsp/src/r_sci_uart/ |
H A D | r_sci_uart.c | 427 uint32_t scr = ((uint8_t) p_extend->clock) & 0x3U; in R_SCI_UART_Open() 1385 if ((SCI_UART_CLOCK_EXT8X == p_extend->clock) || (SCI_UART_CLOCK_EXT16X == p_extend->clock)) in r_sci_uart_config_set() 1390 if (SCI_UART_CLOCK_EXT8X == p_extend->clock) in r_sci_uart_config_set()
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/btstack/port/stm32-l451-miromico-sx1280/ |
H A D | README.md | 18 On the FMLR-80-P-STL4E module, the 52 Mhz clock for the SX1280 is controlled by the MCU.
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/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra_gen/ |
H A D | hal_data.c | 170 { .clock = SCI_UART_CLOCK_INT, .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, .noise_cancel =
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/btstack/port/samv71-xplained-atwilc3000/ASF/sam/drivers/pmc/ |
H A D | sleep.c | 58 # warning The board main clock xtal statup time has not been defined. Using default settings.
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/btstack/port/msp432p401lp-cc256x/ |
H A D | ozone.jdebug | 48 * Typical use: GPIO clock needs to be enabled, before
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/btstack/port/renesas-ek-ra6m4a-da14531/ |
H A D | ozone.jdebug.in | 263 * Typical use: GPIO clock needs to be enabled, before
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/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/ |
H A D | btstack_example.jdebug | 48 * Typical use: GPIO clock needs to be enabled, before
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/btstack/port/stm32-l476rg-nucleo-sx1280/ |
H A D | ozone.jdebug | 262 * Typical use: GPIO clock needs to be enabled, before
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