1 /*
2 * Copyright © 2021 Google
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #define AC_SURFACE_INCLUDE_NIR
8 #include "ac_surface.h"
9
10 #include "radv_meta.h"
11 #include "vk_common_entrypoints.h"
12
13 static nir_shader *
build_dcc_retile_compute_shader(struct radv_device * dev,struct radeon_surf * surf)14 build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *surf)
15 {
16 const struct radv_physical_device *pdev = radv_device_physical(dev);
17 enum glsl_sampler_dim dim = GLSL_SAMPLER_DIM_BUF;
18 const struct glsl_type *buf_type = glsl_image_type(dim, false, GLSL_TYPE_UINT);
19 nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "dcc_retile_compute");
20
21 b.shader->info.workgroup_size[0] = 8;
22 b.shader->info.workgroup_size[1] = 8;
23
24 nir_def *src_dcc_size = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8);
25 nir_def *src_dcc_pitch = nir_channels(&b, src_dcc_size, 1);
26 nir_def *src_dcc_height = nir_channels(&b, src_dcc_size, 2);
27
28 nir_def *dst_dcc_size = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 8), .range = 8);
29 nir_def *dst_dcc_pitch = nir_channels(&b, dst_dcc_size, 1);
30 nir_def *dst_dcc_height = nir_channels(&b, dst_dcc_size, 2);
31 nir_variable *input_dcc = nir_variable_create(b.shader, nir_var_uniform, buf_type, "dcc_in");
32 input_dcc->data.descriptor_set = 0;
33 input_dcc->data.binding = 0;
34 nir_variable *output_dcc = nir_variable_create(b.shader, nir_var_uniform, buf_type, "dcc_out");
35 output_dcc->data.descriptor_set = 0;
36 output_dcc->data.binding = 1;
37
38 nir_def *input_dcc_ref = &nir_build_deref_var(&b, input_dcc)->def;
39 nir_def *output_dcc_ref = &nir_build_deref_var(&b, output_dcc)->def;
40
41 nir_def *coord = get_global_ids(&b, 2);
42 nir_def *zero = nir_imm_int(&b, 0);
43 coord =
44 nir_imul(&b, coord, nir_imm_ivec2(&b, surf->u.gfx9.color.dcc_block_width, surf->u.gfx9.color.dcc_block_height));
45
46 nir_def *src = ac_nir_dcc_addr_from_coord(&b, &pdev->info, surf->bpe, &surf->u.gfx9.color.dcc_equation,
47 src_dcc_pitch, src_dcc_height, zero, nir_channel(&b, coord, 0),
48 nir_channel(&b, coord, 1), zero, zero, zero);
49 nir_def *dst = ac_nir_dcc_addr_from_coord(&b, &pdev->info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation,
50 dst_dcc_pitch, dst_dcc_height, zero, nir_channel(&b, coord, 0),
51 nir_channel(&b, coord, 1), zero, zero, zero);
52
53 nir_def *dcc_val = nir_image_deref_load(&b, 1, 32, input_dcc_ref, nir_vec4(&b, src, src, src, src),
54 nir_undef(&b, 1, 32), nir_imm_int(&b, 0), .image_dim = dim);
55
56 nir_image_deref_store(&b, output_dcc_ref, nir_vec4(&b, dst, dst, dst, dst), nir_undef(&b, 1, 32), dcc_val,
57 nir_imm_int(&b, 0), .image_dim = dim);
58
59 return b.shader;
60 }
61
62 void
radv_device_finish_meta_dcc_retile_state(struct radv_device * device)63 radv_device_finish_meta_dcc_retile_state(struct radv_device *device)
64 {
65 struct radv_meta_state *state = &device->meta_state;
66
67 for (unsigned i = 0; i < ARRAY_SIZE(state->dcc_retile.pipeline); i++) {
68 radv_DestroyPipeline(radv_device_to_handle(device), state->dcc_retile.pipeline[i], &state->alloc);
69 }
70 radv_DestroyPipelineLayout(radv_device_to_handle(device), state->dcc_retile.p_layout, &state->alloc);
71 device->vk.dispatch_table.DestroyDescriptorSetLayout(radv_device_to_handle(device), state->dcc_retile.ds_layout,
72 &state->alloc);
73 }
74
75 /*
76 * This take a surface, but the only things used are:
77 * - BPE
78 * - DCC equations
79 * - DCC block size
80 *
81 * BPE is always 4 at the moment and the rest is derived from the tilemode.
82 */
83 static VkResult
create_pipeline(struct radv_device * device,struct radeon_surf * surf)84 create_pipeline(struct radv_device *device, struct radeon_surf *surf)
85 {
86 VkResult result = VK_SUCCESS;
87
88 if (!device->meta_state.dcc_retile.ds_layout) {
89 const VkDescriptorSetLayoutBinding bindings[] = {
90 {
91 .binding = 0,
92 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
93 .descriptorCount = 1,
94 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
95 },
96 {
97 .binding = 1,
98 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
99 .descriptorCount = 1,
100 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
101 },
102
103 };
104
105 result = radv_meta_create_descriptor_set_layout(device, 2, bindings, &device->meta_state.dcc_retile.ds_layout);
106 if (result != VK_SUCCESS)
107 return result;
108 }
109
110 if (!device->meta_state.dcc_retile.p_layout) {
111 const VkPushConstantRange pc_range = {
112 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
113 .size = 16,
114 };
115
116 result = radv_meta_create_pipeline_layout(device, &device->meta_state.dcc_retile.ds_layout, 1, &pc_range,
117 &device->meta_state.dcc_retile.p_layout);
118 if (result != VK_SUCCESS)
119 return result;
120 }
121
122 nir_shader *cs = build_dcc_retile_compute_shader(device, surf);
123
124 result = radv_meta_create_compute_pipeline(device, cs, device->meta_state.dcc_retile.p_layout,
125 &device->meta_state.dcc_retile.pipeline[surf->u.gfx9.swizzle_mode]);
126
127 ralloc_free(cs);
128 return result;
129 }
130
131 static VkResult
get_pipeline(struct radv_device * device,struct radv_image * image,VkPipeline * pipeline_out)132 get_pipeline(struct radv_device *device, struct radv_image *image, VkPipeline *pipeline_out)
133 {
134 struct radv_meta_state *state = &device->meta_state;
135 VkResult result = VK_SUCCESS;
136
137 const unsigned swizzle_mode = image->planes[0].surface.u.gfx9.swizzle_mode;
138
139 mtx_lock(&state->mtx);
140 if (!state->dcc_retile.pipeline[swizzle_mode]) {
141 result = create_pipeline(device, &image->planes[0].surface);
142 if (result != VK_SUCCESS)
143 goto fail;
144 }
145
146 *pipeline_out = state->dcc_retile.pipeline[swizzle_mode];
147
148 fail:
149 mtx_unlock(&state->mtx);
150 return result;
151 }
152
153 void
radv_retile_dcc(struct radv_cmd_buffer * cmd_buffer,struct radv_image * image)154 radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image)
155 {
156 struct radv_meta_saved_state saved_state;
157 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
158 struct radv_buffer buffer;
159 VkPipeline pipeline;
160 VkResult result;
161
162 assert(image->vk.image_type == VK_IMAGE_TYPE_2D);
163 assert(image->vk.array_layers == 1 && image->vk.mip_levels == 1);
164
165 struct radv_cmd_state *state = &cmd_buffer->state;
166
167 result = get_pipeline(device, image, &pipeline);
168 if (result != VK_SUCCESS) {
169 vk_command_buffer_set_error(&cmd_buffer->vk, result);
170 return;
171 }
172
173 state->flush_bits |=
174 radv_dst_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT, VK_ACCESS_2_SHADER_READ_BIT, image);
175
176 radv_meta_save(&saved_state, cmd_buffer,
177 RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
178
179 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
180
181 radv_buffer_init(&buffer, device, image->bindings[0].bo, image->size, image->bindings[0].offset);
182
183 struct radv_buffer_view views[2];
184 VkBufferView view_handles[2];
185 radv_buffer_view_init(views, device,
186 &(VkBufferViewCreateInfo){
187 .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
188 .buffer = radv_buffer_to_handle(&buffer),
189 .offset = image->planes[0].surface.meta_offset,
190 .range = image->planes[0].surface.meta_size,
191 .format = VK_FORMAT_R8_UINT,
192 });
193 radv_buffer_view_init(views + 1, device,
194 &(VkBufferViewCreateInfo){
195 .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
196 .buffer = radv_buffer_to_handle(&buffer),
197 .offset = image->planes[0].surface.display_dcc_offset,
198 .range = image->planes[0].surface.u.gfx9.color.display_dcc_size,
199 .format = VK_FORMAT_R8_UINT,
200 });
201 for (unsigned i = 0; i < 2; ++i)
202 view_handles[i] = radv_buffer_view_to_handle(&views[i]);
203
204 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, device->meta_state.dcc_retile.p_layout, 0,
205 2,
206 (VkWriteDescriptorSet[]){
207 {
208 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
209 .dstBinding = 0,
210 .dstArrayElement = 0,
211 .descriptorCount = 1,
212 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
213 .pTexelBufferView = &view_handles[0],
214 },
215 {
216 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
217 .dstBinding = 1,
218 .dstArrayElement = 0,
219 .descriptorCount = 1,
220 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
221 .pTexelBufferView = &view_handles[1],
222 },
223 });
224
225 unsigned width = DIV_ROUND_UP(image->vk.extent.width, vk_format_get_blockwidth(image->vk.format));
226 unsigned height = DIV_ROUND_UP(image->vk.extent.height, vk_format_get_blockheight(image->vk.format));
227
228 unsigned dcc_width = DIV_ROUND_UP(width, image->planes[0].surface.u.gfx9.color.dcc_block_width);
229 unsigned dcc_height = DIV_ROUND_UP(height, image->planes[0].surface.u.gfx9.color.dcc_block_height);
230
231 uint32_t constants[] = {
232 image->planes[0].surface.u.gfx9.color.dcc_pitch_max + 1,
233 image->planes[0].surface.u.gfx9.color.dcc_height,
234 image->planes[0].surface.u.gfx9.color.display_dcc_pitch_max + 1,
235 image->planes[0].surface.u.gfx9.color.display_dcc_height,
236 };
237 vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.dcc_retile.p_layout,
238 VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, constants);
239
240 radv_unaligned_dispatch(cmd_buffer, dcc_width, dcc_height, 1);
241
242 radv_buffer_view_finish(views);
243 radv_buffer_view_finish(views + 1);
244 radv_buffer_finish(&buffer);
245
246 radv_meta_restore(&saved_state, cmd_buffer);
247
248 state->flush_bits |=
249 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
250 radv_src_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT, VK_ACCESS_2_SHADER_WRITE_BIT, image);
251 }
252