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/linux-6.14.4/drivers/clocksource/
Dingenic-ost.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
11 #include <linux/mfd/ingenic-tcu.h>
25 * The TCU_REG_OST_CNT{L,R} from <linux/mfd/ingenic-tcu.h> are only for the
37 struct clk *clk; member
39 struct clocksource cs; member
46 /* Read using __iomem pointer instead of regmap to avoid locking */ in ingenic_ost_read_cntl()
47 return readl(ingenic_ost->regs + OST_REG_CNTL); in ingenic_ost_read_cntl()
52 /* Read using __iomem pointer instead of regmap to avoid locking */ in ingenic_ost_read_cnth()
53 return readl(ingenic_ost->regs + OST_REG_CNTH); in ingenic_ost_read_cnth()
[all …]
Dem_sti.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Emma Mobile Timer Support - STI
14 #include <linux/clk.h>
27 struct clk *clk; member
33 struct clocksource cs; member
55 return ioread32(p->base + offs); in em_sti_read()
61 iowrite32(value, p->base + offs); in em_sti_write()
69 ret = clk_enable(p->clk); in em_sti_enable()
71 dev_err(&p->pdev->dev, "cannot enable clock\n"); in em_sti_enable()
95 clk_disable(p->clk); in em_sti_disable()
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Dtimer-sun5i.c1 // SPDX-License-Identifier: GPL-2.0
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
10 #include <linux/clk.h>
38 struct clk *clk; member
53 * When we disable a timer, we need to wait at least for 2 cycles of
60 u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clkevt_sync()
62 while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) in sun5i_clkevt_sync()
68 u32 val = readl(ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
69 writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
76 writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer)); in sun5i_clkevt_time_setup()
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Dsh_tmu.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - TMU
8 #include <linux/clk.h>
47 struct clocksource cs; member
56 struct clk *clk; member
70 #define TSTR -1 /* shared register */
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
100 return ioread16(ch->base + offs); in sh_tmu_read()
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Dtimer-cadence-ttc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Xilinx
10 #include <linux/clk.h>
23 * This driver configures the 2 16/32-bit count-up timers as follows:
29 * The input frequency to the timer module for emulation is 2.5MHz which is
30 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
33 * The input frequency to the timer module in silicon is configurable and
34 * obtained from device tree. The pre-scaler of 32 is used.
55 * Setup the timers to use pre-scaling, using a fixed value for now that will
56 * work across most input frequency, but it may need to be more dynamic
[all …]
Dingenic-timer.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
14 #include <linux/mfd/ingenic-tcu.h>
23 #include <dt-bindings/clock/ingenic,tcu.h>
35 struct clk *clk; member
42 struct clk *cs_clk;
44 struct clocksource cs; member
56 regmap_read(tcu->map, TCU_REG_TCNTc(tcu->cs_channel), &count); in ingenic_tcu_timer_read()
61 static u64 notrace ingenic_tcu_timer_cs_read(struct clocksource *cs) in ingenic_tcu_timer_cs_read() argument
69 return container_of(timer, struct ingenic_tcu, timers[timer->cpu]); in to_ingenic_tcu()
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Dingenic-sysost.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/ingenic,sysost.h>
76 struct clk *clk, *percpu_timer_clk, *global_timer_clk; member
78 struct clocksource cs; member
95 const struct ingenic_ost_clk_info *info = ost_clk->info; in ingenic_ost_percpu_timer_recalc_rate()
98 prescale = readl(ost_clk->ost->base + info->ostccr_reg); in ingenic_ost_percpu_timer_recalc_rate()
109 const struct ingenic_ost_clk_info *info = ost_clk->info; in ingenic_ost_global_timer_recalc_rate()
112 prescale = readl(ost_clk->ost->base + info->ostccr_reg); in ingenic_ost_global_timer_recalc_rate()
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Dsh_cmt.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - CMT
8 #include <linux/clk.h>
39 * 16B 32B 32B-F 48B R-Car Gen2
40 * -----------------------------------------------------------------------------
46 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
50 * Channels are indexed from 0 to N-1 in the documentation. The channel index
55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
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/linux-6.14.4/drivers/memory/
Dti-aemif.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
8 * Murali Karicheri <m-[email protected]>
12 #include <linux/clk.h>
16 #include <linux/memory/ti-aemif.h>
85 * struct aemif_cs_data: structure to hold CS parameters
87 * @cs: chip-select number
94 u8 cs; member
101 * struct aemif_device: structure to hold device data
103 * @clk: source clock
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Dpl172.c1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
13 #include <linux/clk.h>
53 struct clk *clk; member
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
70 return -EINVAL; in pl172_timing_prop()
73 writel(cycles, pl172->base + reg_offset); in pl172_timing_prop()
76 dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start + in pl172_timing_prop()
77 readl(pl172->base + reg_offset)); in pl172_timing_prop()
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Datmel-ebi.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2013 Jean-Jacques Hiblot <[email protected]>
10 #include <linux/clk.h>
13 #include <linux/mfd/syscon/atmel-matrix.h>
14 #include <linux/mfd/syscon/atmel-smc.h>
21 #include <soc/at91/atmel-sfr.h>
26 int cs; member
54 struct clk *clk; member
58 struct clk *clk; member
86 atmel_smc_cs_conf_get(ebid->ebi->smc.regmap, conf->cs, in at91sam9_ebi_get_config()
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Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk.h>
195 struct clk *clk; member
210 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
214 * @reg_type: the register that have to be modified
215 * @reg_mask: the bit that have to be modified in the selected register
217 * @reset_val: the default value that have to be set in case the property
221 * @calculate: this callback is called to calculate for exemple a timing
234 const struct stm32_fmc2_prop *prop, int cs);
235 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
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/linux-6.14.4/drivers/mfd/
Datmel-smc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
18 * Set all fields to 0 so that one can start defining a new config.
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
29 * @ncycles: number of MCK clk cycles
32 * @msbfactor: factor applied to the MSB
33 * @encodedval: param used to store the encoding result
[all …]
/linux-6.14.4/drivers/spi/
Dspi-dw-mmio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
8 #include <linux/clk.h>
24 #include "spi-dw.h"
30 struct clk *clk; member
31 struct clk *pclk;
57 * Elba SoC does not use ssi, pin override is used for cs 0,1 and
58 * gpios for cs 2,3 as defined in the device tree.
60 * cs: | 1 0
61 * bit: |---3-------2-------1-------0
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Dspi-wpcm-fiu.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/clk.h>
10 #include <linux/spi/spi-mem.h>
48 * I observed a typical wait time of 16 iterations for a UMA transfer to
53 /* The memory-mapped view of flash is 16 MiB long */
59 struct clk *clk; member
68 writeb(opcode, fiu->regs + FIU_UMA_CODE); in wpcm_fiu_set_opcode()
73 writeb((addr >> 0) & 0xff, fiu->regs + FIU_UMA_AB0); in wpcm_fiu_set_addr()
74 writeb((addr >> 8) & 0xff, fiu->regs + FIU_UMA_AB1); in wpcm_fiu_set_addr()
75 writeb((addr >> 16) & 0xff, fiu->regs + FIU_UMA_AB2); in wpcm_fiu_set_addr()
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Dspi-bcm2835aux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Based on: spi-bcm2835.c
13 #include <linux/clk.h>
32 "time in us to run a transfer in polling mode - if zero no polling is used\n");
88 struct clk *clk; member
112 snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname); in bcm2835aux_debugfs_create()
116 bs->debugfs_dir = dir; in bcm2835aux_debugfs_create()
120 &bs->count_transfer_polling); in bcm2835aux_debugfs_create()
122 &bs->count_transfer_irq); in bcm2835aux_debugfs_create()
124 &bs->count_transfer_irq_after_poll); in bcm2835aux_debugfs_create()
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Dspi-xlp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2003-2015 Broadcom Corporation
7 #include <linux/clk.h>
98 int cs; /* target device chip select */ member
100 bool cmd_cont; /* cs active */
105 int cs, int regoff) in xlp_spi_reg_read() argument
107 return readl(priv->base + regoff + cs * SPI_CS_OFFSET); in xlp_spi_reg_read()
110 static inline void xlp_spi_reg_write(struct xlp_spi_priv *priv, int cs, in xlp_spi_reg_write() argument
113 writel(val, priv->base + regoff + cs * SPI_CS_OFFSET); in xlp_spi_reg_write()
119 writel(val, priv->base + regoff); in xlp_spi_sysctl_write()
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Dspi-mpc512x-psc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Hongjun Chen <hong-[email protected]>
22 #include <linux/clk.h>
37 switch (mps->type) { \
39 struct mpc52xx_psc __iomem *psc = mps->psc; \
40 __ret = &psc->regname; \
44 struct mpc5125_psc __iomem *psc = mps->psc; \
45 __ret = &psc->regname; \
70 * if t is NULL then reset the values to the default values
75 struct mpc512x_psc_spi_cs *cs = spi->controller_state; in mpc512x_psc_spi_transfer_setup() local
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Dspi-orion.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2007-2008 Marvell Ltd.
19 #include <linux/clk.h>
28 /* Some SoCs using this driver support up to 8 chip selects.
29 * It is up to the implementer to only use the chip selects
61 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \ argument
73 * have both is for managing the armada-370-spi case with old
95 struct clk *clk; member
96 struct clk *axi_clk;
110 return orion_spi->base + reg; in spi_reg()
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Dspi-bcm63xx-hsspi.c4 * Copyright 2000-2010 Broadcom Corporation
5 * Copyright 2012-2013 Jonas Gorski <[email protected]>
13 #include <linux/clk.h>
17 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi-mem.h>
24 #include <linux/mtd/spi-nor.h>
99 * Some chip require 30MHz but other require 25MHz. Use smaller value to cover
114 * mode. If not, falls back to use the dummy cs workaround mode but limit the
115 * clock to 25MHz to make sure it works in all board design.
124 if (bs->xfer_mode == HSSPI_XFER_MODE_AUTO) \
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/linux-6.14.4/include/linux/platform_data/
Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
39 /* ADV signal timings corresponding to GPMC_CONFIG3 */
47 /* WE signals timings corresponding to GPMC_CONFIG4 */
51 /* OE signals timings corresponding to GPMC_CONFIG4 */
57 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
59 u32 access; /* Start-cycle to first data valid delay */
78 u32 t_ceasu; /* address setup to CS valid */
79 u32 t_avdasu; /* address setup to ADV valid */
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/linux-6.14.4/Documentation/devicetree/bindings/memory-controllers/fsl/
Dfsl,imx-weim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <[email protected]>
11 - Sascha Hauer <[email protected]>
16 wireless and mobile applications that use low-power technology. The actual
21 pattern: "^memory-controller@[0-9a-f]+$"
25 - enum:
26 - fsl,imx1-weim
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/linux-6.14.4/drivers/bus/
Dimx-weim.c11 #include <linux/clk.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
68 struct cs_timing cs[MAX_CS_COUNT]; member
78 { .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
80 { .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
82 { .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
83 { .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
85 { .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
92 struct device_node *np = pdev->dev.of_node; in imx_weim_gpr_setup()
104 int cs = 0; in imx_weim_gpr_setup() local
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Dqcom-ebi2.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
43 * Inserted when reading one CS and switching to another CS or read
44 * followed by write on the same CS. Valid values 0 thru 15.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
47 * asserted until CS is asserted. With a hold of 1, the CS stays
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
50 * write to a page or burst memory
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/linux-6.14.4/drivers/mtd/nand/raw/
Dintel-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0+
4 #include <linux/clk.h>
7 #include <linux/dma-direction.h>
8 #include <linux/dma-mapping.h>
121 struct clk *clk; member
124 struct ebu_nand_cs cs[MAX_CS]; member
137 return readl_poll_timeout(ctrl->ebu + EBU_WAIT, status, in ebu_nand_waitrdy()
145 u8 cs_num = ebu_host->cs_num; in ebu_nand_readb()
148 val = readb(ebu_host->cs[cs_num].chipaddr + HSNAND_CS_OFFS); in ebu_nand_readb()
156 u8 cs_num = ebu_host->cs_num; in ebu_nand_writeb()
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