xref: /XiangShan/src/main/scala/system/SoC.scala (revision 708ceed4afe43fb0ea3a52407e46b2794c573634) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import xiangshan.{DebugOptionsKey, HasXSParameter, XSBundle, XSCore, XSCoreParameters}
23import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, L1BusErrors}
24import huancun.{CacheParameters, HCCacheParameters}
25
26case object SoCParamsKey extends Field[SoCParameters]
27
28case class SoCParameters
29(
30  cores: List[XSCoreParameters],
31  EnableILA: Boolean = false,
32  extIntrs: Int = 150,
33  L3NBanks: Int = 4,
34  L3CacheParams: HCCacheParameters = HCCacheParameters(
35    name = "l3",
36    level = 3,
37    ways = 8,
38    sets = 2048 // 1MB per bank
39  ),
40  useFakeL3Cache: Boolean = false,
41){
42  val PAddrBits = cores.map(_.PAddrBits).reduce((x, y) => if(x > y) x else y)
43  // L3 configurations
44  val L3InnerBusWidth = 256
45  val L3BlockSize = 64
46  // on chip network configurations
47  val L3OuterBusWidth = 256
48}
49
50trait HasSoCParameter {
51  implicit val p: Parameters
52
53  val soc = p(SoCParamsKey)
54  val debugOpts = p(DebugOptionsKey)
55  val NumCores = soc.cores.size
56  val EnableILA = soc.EnableILA
57
58  // L3 configurations
59  val useFakeL3Cache = soc.useFakeL3Cache
60  val L3InnerBusWidth = soc.L3InnerBusWidth
61  val L3BlockSize = soc.L3BlockSize
62  val L3NBanks = soc.L3NBanks
63
64  // on chip network configurations
65  val L3OuterBusWidth = soc.L3OuterBusWidth
66
67  val NrExtIntr = soc.extIntrs
68}
69
70class ILABundle extends Bundle {}
71
72
73class L1CacheErrorInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
74  val paddr = Valid(UInt(soc.PAddrBits.W))
75  // for now, we only detect ecc
76  val ecc_error = Valid(Bool())
77}
78
79class XSL1BusErrors(val nCores: Int)(implicit val p: Parameters) extends BusErrors {
80  val icache = Vec(nCores, new L1CacheErrorInfo)
81  val l1plus = Vec(nCores, new L1CacheErrorInfo)
82  val dcache = Vec(nCores, new L1CacheErrorInfo)
83
84  override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] =
85    List.tabulate(nCores){i =>
86      List(
87        Some(icache(i).paddr, s"IBUS_$i", s"Icache_$i bus error"),
88        Some(icache(i).ecc_error, s"I_ECC_$i", s"Icache_$i ecc error"),
89        Some(l1plus(i).paddr, s"L1PLUS_$i", s"L1PLUS_$i bus error"),
90        Some(l1plus(i).ecc_error, s"L1PLUS_ECC_$i", s"L1PLUS_$i ecc error"),
91        Some(dcache(i).paddr, s"DBUS_$i", s"Dcache_$i bus error"),
92        Some(dcache(i).ecc_error, s"D_ECC_$i", s"Dcache_$i ecc error")
93      )
94    }.flatten
95}
96