xref: /XiangShan/src/main/scala/system/SoC.scala (revision a4e57ea3a91431261d57a58df4810c0d9f0366ef) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO}
23import freechips.rocketchip.devices.tilelink.{CLINT, CLINTParams, DevNullParams, PLICParams, TLError, TLPLIC}
24import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
25import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
26import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup}
27import utils.{BinaryArbiter, TLEdgeBuffer}
28import xiangshan.{DebugOptionsKey, HasXSParameter, XSBundle, XSCore, XSCoreParameters, XSTileKey}
29import freechips.rocketchip.amba.axi4._
30import freechips.rocketchip.tilelink._
31import top.BusPerfMonitor
32import xiangshan.backend.fu.PMAConst
33import huancun._
34import huancun.debug.TLLogger
35
36case object SoCParamsKey extends Field[SoCParameters]
37
38case class SoCParameters
39(
40  EnableILA: Boolean = false,
41  PAddrBits: Int = 36,
42  extIntrs: Int = 64,
43  L3NBanks: Int = 4,
44  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
45    name = "l3",
46    level = 3,
47    ways = 8,
48    sets = 2048 // 1MB per bank
49  ))
50){
51  // L3 configurations
52  val L3InnerBusWidth = 256
53  val L3BlockSize = 64
54  // on chip network configurations
55  val L3OuterBusWidth = 256
56}
57
58trait HasSoCParameter {
59  implicit val p: Parameters
60
61  val soc = p(SoCParamsKey)
62  val debugOpts = p(DebugOptionsKey)
63  val tiles = p(XSTileKey)
64
65  val NumCores = tiles.size
66  val EnableILA = soc.EnableILA
67
68  // L3 configurations
69  val L3InnerBusWidth = soc.L3InnerBusWidth
70  val L3BlockSize = soc.L3BlockSize
71  val L3NBanks = soc.L3NBanks
72
73  // on chip network configurations
74  val L3OuterBusWidth = soc.L3OuterBusWidth
75
76  val NrExtIntr = soc.extIntrs
77}
78
79class ILABundle extends Bundle {}
80
81
82abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
83  val bankedNode = BankBinder(L3NBanks, L3BlockSize)
84  val peripheralXbar = TLXbar()
85  val l3_xbar = TLXbar()
86  val l3_banked_xbar = TLXbar()
87}
88
89// We adapt the following three traits from rocket-chip.
90// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
91trait HaveSlaveAXI4Port {
92  this: BaseSoC =>
93
94  val idBits = 14
95
96  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
97    Seq(AXI4MasterParameters(
98      name = "dma",
99      id = IdRange(0, 1 << idBits)
100    ))
101  )))
102  private val errorDevice = LazyModule(new TLError(
103    params = DevNullParams(
104      address = Seq(AddressSet(0x0, 0x7fffffffL)),
105      maxAtomic = 8,
106      maxTransfer = 64),
107    beatBytes = L3InnerBusWidth / 8
108  ))
109  private val error_xbar = TLXbar()
110
111  error_xbar :=
112    TLFIFOFixer() :=
113    TLWidthWidget(32) :=
114    AXI4ToTL() :=
115    AXI4UserYanker(Some(1)) :=
116    AXI4Fragmenter() :=
117    AXI4Buffer() :=
118    AXI4Buffer() :=
119    AXI4IdIndexer(1) :=
120    l3FrontendAXI4Node
121  errorDevice.node := error_xbar
122  l3_xbar :=
123    TLBuffer() :=
124    error_xbar
125
126  val dma = InModuleBody {
127    l3FrontendAXI4Node.makeIOs()
128  }
129}
130
131trait HaveAXI4MemPort {
132  this: BaseSoC =>
133  val device = new MemoryDevice
134  // 36-bit physical address
135  val memRange = AddressSet(0x00000000L, 0xfffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
136  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
137    AXI4SlavePortParameters(
138      slaves = Seq(
139        AXI4SlaveParameters(
140          address = memRange,
141          regionType = RegionType.UNCACHED,
142          executable = true,
143          supportsRead = TransferSizes(1, L3BlockSize),
144          supportsWrite = TransferSizes(1, L3BlockSize),
145          interleavedId = Some(0),
146          resources = device.reg("mem")
147        )
148      ),
149      beatBytes = L3OuterBusWidth / 8
150    )
151  ))
152
153  val mem_xbar = TLXbar()
154  mem_xbar :=*
155    TLXbar() :=*
156    TLEdgeBuffer(i => i == 0, Some("L3EdgeBuffer_1")) :=*
157    BinaryArbiter() :=*
158    TLEdgeBuffer(i => i == 0, Some("L3EdgeBuffer_0")) :=*
159    TLCacheCork() :=*
160    bankedNode
161
162  mem_xbar :=
163    TLWidthWidget(8) :=
164    TLBuffer.chainNode(5, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
165    peripheralXbar
166
167  memAXI4SlaveNode :=
168    AXI4Buffer() :=
169    AXI4IdIndexer(idBits = 14) :=
170    AXI4UserYanker() :=
171    AXI4Deinterleaver(L3BlockSize) :=
172    TLToAXI4() :=
173    TLSourceShrinker(64) :=
174    TLWidthWidget(L3OuterBusWidth / 8) :=
175    TLEdgeBuffer(_ => true, Some("MemXbar_to_DDR_buffer")) :=
176    mem_xbar
177
178  val memory = InModuleBody {
179    memAXI4SlaveNode.makeIOs()
180  }
181}
182
183trait HaveAXI4PeripheralPort { this: BaseSoC =>
184  // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
185  val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
186  val uartRange = AddressSet(0x40600000, 0xf)
187  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
188  val uartParams = AXI4SlaveParameters(
189    address = Seq(uartRange),
190    regionType = RegionType.UNCACHED,
191    supportsRead = TransferSizes(1, 8),
192    supportsWrite = TransferSizes(1, 8),
193    resources = uartDevice.reg
194  )
195  val peripheralRange = AddressSet(
196    0x0, 0x7fffffff
197  ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
198  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
199    Seq(AXI4SlaveParameters(
200      address = peripheralRange,
201      regionType = RegionType.UNCACHED,
202      supportsRead = TransferSizes(1, 8),
203      supportsWrite = TransferSizes(1, 8),
204      interleavedId = Some(0)
205    ), uartParams),
206    beatBytes = 8
207  )))
208
209  peripheralNode :=
210    AXI4IdIndexer(idBits = 2) :=
211    AXI4Buffer() :=
212    AXI4Buffer() :=
213    AXI4Buffer() :=
214    AXI4Buffer() :=
215    AXI4UserYanker() :=
216    AXI4Deinterleaver(8) :=
217    TLToAXI4() :=
218    TLBuffer() :=
219    peripheralXbar
220
221  val peripheral = InModuleBody {
222    peripheralNode.makeIOs()
223  }
224
225}
226
227class SoCMisc()(implicit p: Parameters) extends BaseSoC
228  with HaveAXI4MemPort
229  with HaveAXI4PeripheralPort
230  with PMAConst
231  with HaveSlaveAXI4Port
232{
233  val peripheral_ports = Array.fill(NumCores) { TLTempNode() }
234  val core_to_l3_ports = Array.fill(NumCores) { TLTempNode() }
235
236  val l3_in = TLTempNode()
237  val l3_out = TLTempNode()
238  val l3_mem_pmu = BusPerfMonitor(enable = !debugOpts.FPGAPlatform)
239
240  l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar
241  bankedNode :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform) :*= l3_mem_pmu :*= l3_out
242
243  if(soc.L3CacheParamsOpt.isEmpty){
244    l3_out :*= l3_in
245  }
246
247  for(port <- peripheral_ports) {
248    peripheralXbar := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
249  }
250
251  for ((core_out, i) <- core_to_l3_ports.zipWithIndex){
252    l3_banked_xbar :=*
253      TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform) :=*
254      TLBuffer() :=
255      core_out
256  }
257  l3_banked_xbar := TLBuffer() := l3_xbar
258
259  val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
260  clint.node := peripheralXbar
261
262  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
263    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
264    lazy val module = new LazyModuleImp(this){
265      val in = IO(Input(Vec(num, Bool())))
266      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
267    }
268  }
269
270  val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
271  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
272
273  plic.intnode := plicSource.sourceNode
274  plic.node := peripheralXbar
275
276  val pll_node = TLRegisterNode(
277    address = Seq(AddressSet(0x3a000000L, 0xfff)),
278    device = new SimpleDevice("pll_ctrl", Seq()),
279    beatBytes = 8,
280    concurrency = 1
281  )
282  pll_node := peripheralXbar
283
284  val debugModule = LazyModule(new DebugModule(NumCores)(p))
285  debugModule.debug.node := peripheralXbar
286  debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
287    l3_xbar := TLBuffer() := TLWidthWidget(1) := sb2tl.node
288  }
289
290  val pma = LazyModule(new TLPMA)
291  pma.node := peripheralXbar
292
293  lazy val module = new LazyModuleImp(this){
294
295    val debug_module_io = IO(chiselTypeOf(debugModule.module.io))
296    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
297    val pll0_lock = IO(Input(Bool()))
298    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
299    val cacheable_check = IO(new TLPMAIO)
300
301    val ext_intrs_sync = RegNext(RegNext(RegNext(ext_intrs)))
302    val ext_intrs_wire = Wire(UInt(NrExtIntr.W))
303    ext_intrs_wire := ext_intrs_sync
304    debugModule.module.io <> debug_module_io
305    plicSource.module.in := ext_intrs_wire.asBools
306    pma.module.io <> cacheable_check
307
308    val freq = 100
309    val cnt = RegInit(freq.U)
310    val tick = cnt === 0.U
311    cnt := Mux(tick, freq.U, cnt - 1.U)
312    clint.module.io.rtcTick := tick
313
314    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
315    val pll_lock = RegNext(next = pll0_lock, init = false.B)
316
317    pll0_ctrl <> VecInit(pll_ctrl_regs)
318
319    pll_node.regmap(
320      0x000 -> RegFieldGroup(
321        "Pll", Some("PLL ctrl regs"),
322        pll_ctrl_regs.zipWithIndex.map{
323          case (r, i) => RegField(32, r, RegFieldDesc(
324            s"PLL_ctrl_$i",
325            desc = s"PLL ctrl register #$i"
326          ))
327        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
328          "PLL_lock",
329          "PLL lock register"
330        ))
331      )
332    )
333  }
334}
335