xref: /XiangShan/src/main/scala/system/SoC.scala (revision c679fdb3e06d28640309a8c9a3da397a89cf624c) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.DebugModule
23import freechips.rocketchip.amba.axi4.{AXI4Buffer, AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4MasterNode, AXI4MasterParameters, AXI4MasterPortParameters, AXI4SlaveNode, AXI4SlaveParameters, AXI4SlavePortParameters, AXI4ToTL, AXI4UserYanker}
24import freechips.rocketchip.devices.tilelink.{CLINT, CLINTParams, DevNullParams, PLICParams, TLError, TLPLIC}
25import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
26import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
27import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup}
28import xiangshan.{DebugOptionsKey, HasXSParameter, XSBundle, XSCore, XSCoreParameters, XSTileKey}
29import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, L1BusErrors}
30import freechips.rocketchip.tilelink.{BankBinder, TLBuffer, TLCacheCork, TLFIFOFixer, TLRegisterNode, TLTempNode, TLToAXI4, TLWidthWidget, TLXbar}
31import huancun.debug.TLLogger
32import huancun.{BankedXbar, CacheParameters, HCCacheParameters}
33import top.BusPerfMonitor
34import utils.{BinaryArbiter, TLEdgeBuffer}
35
36case object SoCParamsKey extends Field[SoCParameters]
37
38case class SoCParameters
39(
40  EnableILA: Boolean = false,
41  PAddrBits: Int = 36,
42  extIntrs: Int = 64,
43  L3NBanks: Int = 4,
44  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
45    name = "l3",
46    level = 3,
47    ways = 8,
48    sets = 2048 // 1MB per bank
49  ))
50){
51  // L3 configurations
52  val L3InnerBusWidth = 256
53  val L3BlockSize = 64
54  // on chip network configurations
55  val L3OuterBusWidth = 256
56}
57
58trait HasSoCParameter {
59  implicit val p: Parameters
60
61  val soc = p(SoCParamsKey)
62  val debugOpts = p(DebugOptionsKey)
63  val tiles = p(XSTileKey)
64
65  val NumCores = tiles.size
66  val EnableILA = soc.EnableILA
67
68  // L3 configurations
69  val L3InnerBusWidth = soc.L3InnerBusWidth
70  val L3BlockSize = soc.L3BlockSize
71  val L3NBanks = soc.L3NBanks
72
73  // on chip network configurations
74  val L3OuterBusWidth = soc.L3OuterBusWidth
75
76  val NrExtIntr = soc.extIntrs
77}
78
79class ILABundle extends Bundle {}
80
81
82abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
83  val bankedNode = BankBinder(L3NBanks, L3BlockSize)
84  val peripheralXbar = TLXbar()
85  val l3_xbar = TLXbar()
86  val l3_banked_xbar = BankedXbar(tiles.head.L2NBanks)
87}
88
89// We adapt the following three traits from rocket-chip.
90// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
91trait HaveSlaveAXI4Port {
92  this: BaseSoC =>
93
94  val idBits = 14
95
96  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
97    Seq(AXI4MasterParameters(
98      name = "dma",
99      id = IdRange(0, 1 << idBits)
100    ))
101  )))
102  private val errorDevice = LazyModule(new TLError(
103    params = DevNullParams(
104      address = Seq(AddressSet(0x0, 0x7fffffffL)),
105      maxAtomic = 8,
106      maxTransfer = 64),
107    beatBytes = L3InnerBusWidth / 8
108  ))
109  private val error_xbar = TLXbar()
110
111  error_xbar :=
112    TLFIFOFixer() :=
113    TLWidthWidget(16) :=
114    AXI4ToTL() :=
115    AXI4UserYanker(Some(1)) :=
116    AXI4Fragmenter() :=
117    AXI4IdIndexer(1) :=
118    l3FrontendAXI4Node
119  errorDevice.node := error_xbar
120  l3_xbar :=
121    TLBuffer() :=
122    error_xbar
123
124  val dma = InModuleBody {
125    l3FrontendAXI4Node.makeIOs()
126  }
127}
128
129trait HaveAXI4MemPort {
130  this: BaseSoC =>
131  val device = new MemoryDevice
132  // 36-bit physical address
133  val memRange = AddressSet(0x00000000L, 0xfffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
134  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
135    AXI4SlavePortParameters(
136      slaves = Seq(
137        AXI4SlaveParameters(
138          address = memRange,
139          regionType = RegionType.UNCACHED,
140          executable = true,
141          supportsRead = TransferSizes(1, L3BlockSize),
142          supportsWrite = TransferSizes(1, L3BlockSize),
143          interleavedId = Some(0),
144          resources = device.reg("mem")
145        )
146      ),
147      beatBytes = L3OuterBusWidth / 8
148    )
149  ))
150
151  val mem_xbar = TLXbar()
152  mem_xbar :=*
153    TLXbar() :=*
154    TLEdgeBuffer(i => i == 0, Some("L3EdgeBuffer_1")) :=*
155    BinaryArbiter() :=*
156    TLEdgeBuffer(i => i == 0, Some("L3EdgeBuffer_0")) :=*
157    TLCacheCork() :=*
158    bankedNode
159
160  mem_xbar :=
161    TLWidthWidget(8) :=
162    TLBuffer.chainNode(5, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
163    peripheralXbar
164
165  memAXI4SlaveNode :=
166    AXI4UserYanker() :=
167    AXI4Deinterleaver(L3BlockSize) :=
168    TLToAXI4() :=
169    TLWidthWidget(L3OuterBusWidth / 8) :=
170    TLEdgeBuffer(_ => true, Some("MemXbar_to_DDR_buffer")) :=
171    mem_xbar
172
173  val memory = InModuleBody {
174    memAXI4SlaveNode.makeIOs()
175  }
176}
177
178trait HaveAXI4PeripheralPort { this: BaseSoC =>
179  // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
180  val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
181  val uartRange = AddressSet(0x40600000, 0xf)
182  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
183  val uartParams = AXI4SlaveParameters(
184    address = Seq(uartRange),
185    regionType = RegionType.UNCACHED,
186    supportsRead = TransferSizes(1, 8),
187    supportsWrite = TransferSizes(1, 8),
188    resources = uartDevice.reg
189  )
190  val peripheralRange = AddressSet(
191    0x0, 0x7fffffff
192  ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
193  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
194    Seq(AXI4SlaveParameters(
195      address = peripheralRange,
196      regionType = RegionType.UNCACHED,
197      supportsRead = TransferSizes(1, 8),
198      supportsWrite = TransferSizes(1, 8),
199      interleavedId = Some(0)
200    ), uartParams),
201    beatBytes = 8
202  )))
203
204  peripheralNode :=
205    AXI4UserYanker() :=
206    AXI4Deinterleaver(8) :=
207    TLToAXI4() :=
208    peripheralXbar
209
210  val peripheral = InModuleBody {
211    peripheralNode.makeIOs()
212  }
213
214}
215
216class SoCMisc()(implicit p: Parameters) extends BaseSoC
217  with HaveAXI4MemPort
218  with HaveAXI4PeripheralPort
219  with HaveSlaveAXI4Port
220{
221  val peripheral_ports = Array.fill(NumCores) { TLTempNode() }
222  val core_to_l3_ports = Array.fill(NumCores) { TLTempNode() }
223
224  val l3_in = TLTempNode()
225  val l3_out = TLTempNode()
226  val l3_mem_pmu = BusPerfMonitor(enable = !debugOpts.FPGAPlatform)
227
228  l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar
229  bankedNode :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform) :*= l3_mem_pmu :*= l3_out
230
231  if(soc.L3CacheParamsOpt.isEmpty){
232    l3_out :*= l3_in
233  }
234
235  for(port <- peripheral_ports) {
236    peripheralXbar := port
237  }
238
239  for ((core_out, i) <- core_to_l3_ports.zipWithIndex){
240    l3_banked_xbar :=*
241      TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform) :=*
242      TLEdgeBuffer(idx => {
243        /*
244                  Core0     Core1
245            _____________________________
246           | L3   B0, B2     B1,B3      |
247            -----------------------------
248
249            Core(i)          0         1
250            Port(idx)      0   1     0  1
251            Buffer?        N   Y     Y  N
252         */
253        val insert_buffer = (i % 2) != (idx % 2)
254        insert_buffer
255      }, Some(s"core_${i}_to_l3_buffer")) :=* core_out
256  }
257  l3_banked_xbar :=* BankBinder(tiles.head.L2NBanks, L3BlockSize) :*= l3_xbar
258
259  val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
260  clint.node := peripheralXbar
261
262  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
263    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
264    lazy val module = new LazyModuleImp(this){
265      val in = IO(Input(Vec(num, Bool())))
266      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
267    }
268  }
269
270  val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
271  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
272
273  plic.intnode := plicSource.sourceNode
274  plic.node := peripheralXbar
275
276  val pll_node = TLRegisterNode(
277    address = Seq(AddressSet(0x3a000000L, 0xfff)),
278    device = new SimpleDevice("pll_ctrl", Seq()),
279    beatBytes = 8,
280    concurrency = 1
281  )
282  pll_node := peripheralXbar
283
284  val debugModule = LazyModule(new DebugModule(NumCores)(p))
285  debugModule.debug.node := peripheralXbar
286  debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
287    l3_xbar := TLBuffer() := TLWidthWidget(1) := sb2tl.node
288  }
289
290  lazy val module = new LazyModuleImp(this){
291
292    val debug_module_io = IO(chiselTypeOf(debugModule.module.io))
293    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
294    val pll0_lock = IO(Input(Bool()))
295    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
296
297    val ext_intrs_sync = RegNext(RegNext(RegNext(ext_intrs)))
298    val ext_intrs_wire = Wire(UInt(NrExtIntr.W))
299    ext_intrs_wire := ext_intrs_sync
300    debugModule.module.io <> debug_module_io
301    plicSource.module.in := ext_intrs_wire.asBools
302
303    val freq = 100
304    val cnt = RegInit(freq.U)
305    val tick = cnt === 0.U
306    cnt := Mux(tick, freq.U, cnt - 1.U)
307    clint.module.io.rtcTick := tick
308
309    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
310    val pll_lock = RegNext(next = pll0_lock, init = false.B)
311
312    pll0_ctrl <> VecInit(pll_ctrl_regs)
313
314    pll_node.regmap(
315      0x000 -> RegFieldGroup(
316        "Pll", Some("PLL ctrl regs"),
317        pll_ctrl_regs.zipWithIndex.map{
318          case (r, i) => RegField(32, r, RegFieldDesc(
319            s"PLL_ctrl_$i",
320            desc = s"PLL ctrl register #$i"
321          ))
322        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
323          "PLL_lock",
324          "PLL lock register"
325        ))
326      )
327    )
328  }
329}
330