1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package utils 18 19import chisel3._ 20import chisel3.util._ 21import chisel3.experimental.dataview._ 22import scala.collection.immutable._ 23import freechips.rocketchip.amba.axi4._ 24 25class VerilogAXI4Record(val params: AXI4BundleParameters) extends Record { 26 private val axi4Bundle = new AXI4Bundle(params) 27 private def traverseAndMap(data: (String, Data)): SeqMap[String, Data] = { 28 data match { 29 case (name: String, node: Bundle) => SeqMap.from( 30 node.elements.map(x => traverseAndMap(x)).flatten.map { 31 case (nodeName, node) => (s"${name.replace("bits", "")}${nodeName}", node) 32 } 33 ) 34 case (name: String, node: Data) => SeqMap(name -> node) 35 } 36 } 37 private val outputPattern = "^(aw|w|ar).*".r 38 private val elems = traverseAndMap("", axi4Bundle) map { case (name, node) => name match { 39 case outputPattern(_) => (name, Output(node)) 40 case _: String => (name, Input (node)) 41 }} map { case (name, node) => name match { 42 case s"${_}ready" => (name, Flipped(node)) 43 case _: String => (name, node) 44 }} 45 def elements: SeqMap[String, Data] = elems 46} 47 48object VerilogAXI4Record { 49 private val elementsMap: Seq[(VerilogAXI4Record, AXI4Bundle) => (Data, Data)] = { 50 val names = (new VerilogAXI4Record(AXI4BundleParameters(1, 8, 1))).elements.map(_._1) 51 val pattern = "^(aw|w|b|ar|r)(.*)".r 52 names.map { name => { (verilog: VerilogAXI4Record, chisel: AXI4Bundle) => { 53 val (channel: Record, signal: String) = name match { 54 case pattern(prefix, signal) => 55 (chisel.elements(prefix).asInstanceOf[Record], signal) 56 case _: String => require(false, "unexpected prefix"); null 57 } 58 verilog.elements(name) -> channel.elements.applyOrElse(signal, 59 channel.elements("bits").asInstanceOf[Record].elements) 60 }}}.toSeq 61 } 62 implicit val axi4View: DataView[VerilogAXI4Record, AXI4Bundle] = DataView[VerilogAXI4Record, AXI4Bundle]( 63 vab => new AXI4Bundle(vab.params), elementsMap: _* 64 ) 65 implicit val axi4View2: DataView[AXI4Bundle, VerilogAXI4Record] = axi4View.invert(ab => new VerilogAXI4Record(ab.params)) 66} 67