1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.brq.BrqPtr 7import xiangshan.backend.rename.FreeListPtr 8 9// Fetch FetchWidth x 32-bit insts from Icache 10class FetchPacket extends XSBundle { 11 val instrs = Vec(FetchWidth, UInt(32.W)) 12 val mask = UInt((FetchWidth*2).W) 13 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 14 val pnpc = Vec(FetchWidth*2, UInt(VAddrBits.W)) 15 val hist = Vec(FetchWidth*2, UInt(HistoryLength.W)) 16 // val btbVictimWay = UInt(log2Up(BtbWays).W) 17 val predCtr = Vec(FetchWidth*2, UInt(2.W)) 18 val btbHit = Vec(FetchWidth*2, Bool()) 19 val tageMeta = Vec(FetchWidth*2, (new TageMeta)) 20 val rasSp = UInt(log2Up(RasSize).W) 21 val rasTopCtr = UInt(8.W) 22} 23 24 25class ValidUndirectioned[T <: Data](gen: T) extends Bundle { 26 val valid = Bool() 27 val bits = gen.asInstanceOf[T] 28 override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type] 29} 30 31object ValidUndirectioned { 32 def apply[T <: Data](gen: T) = { 33 new ValidUndirectioned[T](gen) 34 } 35} 36 37class TageMeta extends XSBundle { 38// val provider = ValidUndirectioned(UInt(log2Ceil(TageNTables).W)) 39 val altDiffers = Bool() 40 val providerU = UInt(2.W) 41 val providerCtr = UInt(3.W) 42// val allocate = ValidUndirectioned(UInt(log2Ceil(TageNTables).W)) 43} 44 45// Branch prediction result from BPU Stage1 & 3 46class BranchPrediction extends XSBundle { 47 val redirect = Bool() 48 49 // mask off all the instrs after the first redirect instr 50 val instrValid = Vec(FetchWidth*2, Bool()) 51 // target of the first redirect instr in a fetch package 52 val target = UInt(VAddrBits.W) 53 val lateJump = Bool() 54 // save these info in brq! 55 // global history of each valid(or uncancelled) instruction, excluding branch's own prediction result 56 val hist = Vec(FetchWidth*2, UInt(HistoryLength.W)) 57 // victim way when updating btb 58 // val btbVictimWay = UInt(log2Up(BtbWays).W) 59 // 2-bit saturated counter 60 val predCtr = Vec(FetchWidth*2, UInt(2.W)) 61 val btbHit = Vec(FetchWidth*2, Bool()) 62 // tage meta info 63 val tageMeta = Vec(FetchWidth*2, (new TageMeta)) 64 // ras checkpoint, only used in Stage3 65 val rasSp = UInt(log2Up(RasSize).W) 66 val rasTopCtr = UInt(8.W) 67} 68 69// Save predecode info in icache 70class Predecode extends XSBundle { 71 val mask = UInt((FetchWidth*2).W) 72 val isRVC = Vec(FetchWidth*2, Bool()) 73 val fuTypes = Vec(FetchWidth*2, FuType()) 74 val fuOpTypes = Vec(FetchWidth*2, FuOpType()) 75} 76 77 78class BranchUpdateInfo extends XSBundle { 79 val fetchOffset = UInt(log2Up(FetchWidth * 4).W) 80 val pnpc = UInt(VAddrBits.W) 81 val brTarget = UInt(VAddrBits.W) 82 val hist = UInt(HistoryLength.W) 83 val btbPredCtr = UInt(2.W) 84 val btbHit = Bool() 85 val tageMeta = new TageMeta 86 val rasSp = UInt(log2Up(RasSize).W) 87 val rasTopCtr = UInt(8.W) 88 val taken = Bool() 89 val fetchIdx = UInt(log2Up(FetchWidth*2).W) 90 val btbType = UInt(2.W) 91 val isRVC = Bool() 92 val isBr = Bool() 93 val isMisPred = Bool() 94} 95 96// Dequeue DecodeWidth insts from Ibuffer 97class CtrlFlow extends XSBundle { 98 val instr = UInt(32.W) 99 val pc = UInt(VAddrBits.W) 100 val exceptionVec = Vec(16, Bool()) 101 val intrVec = Vec(12, Bool()) 102 val brUpdate = new BranchUpdateInfo 103 val crossPageIPFFix = Bool() 104} 105 106// Decode DecodeWidth insts at Decode Stage 107class CtrlSignals extends XSBundle { 108 val src1Type, src2Type, src3Type = SrcType() 109 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 110 val ldest = UInt(5.W) 111 val fuType = FuType() 112 val fuOpType = FuOpType() 113 val rfWen = Bool() 114 val fpWen = Bool() 115 val isXSTrap = Bool() 116 val noSpecExec = Bool() // This inst can not be speculated 117 val isBlocked = Bool() // This inst requires pipeline to be blocked 118 val isRVF = Bool() 119 val imm = UInt(XLEN.W) 120} 121 122class CfCtrl extends XSBundle { 123 val cf = new CtrlFlow 124 val ctrl = new CtrlSignals 125 val brTag = new BrqPtr 126} 127 128trait HasRoqIdx { this: HasXSParameter => 129 val roqIdx = UInt(RoqIdxWidth.W) 130 131 def isAfter(thatIdx: UInt): Bool = { 132 Mux( 133 this.roqIdx.head(1) === thatIdx.head(1), 134 this.roqIdx.tail(1) > thatIdx.tail(1), 135 this.roqIdx.tail(1) < thatIdx.tail(1) 136 ) 137 } 138 139 def needFlush(redirect: Valid[Redirect]): Bool = { 140 redirect.valid && this.isAfter(redirect.bits.roqIdx) 141 } 142} 143 144// CfCtrl -> MicroOp at Rename Stage 145class MicroOp extends CfCtrl with HasRoqIdx { 146 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 147 val src1State, src2State, src3State = SrcState() 148 val moqIdx = UInt(MoqIdxWidth.W) 149} 150 151class Redirect extends XSBundle with HasRoqIdx { 152 val isException = Bool() 153 val isMisPred = Bool() 154 val isReplay = Bool() 155 val pc = UInt(VAddrBits.W) 156 val target = UInt(VAddrBits.W) 157 val brTag = new BrqPtr 158} 159 160class Dp1ToDp2IO extends XSBundle { 161 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 162 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 163 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 164} 165 166class DebugBundle extends XSBundle{ 167 val isMMIO = Bool() 168} 169 170class ExuInput extends XSBundle { 171 val uop = new MicroOp 172 val src1, src2, src3 = UInt(XLEN.W) 173} 174 175class ExuOutput extends XSBundle { 176 val uop = new MicroOp 177 val data = UInt(XLEN.W) 178 val redirectValid = Bool() 179 val redirect = new Redirect 180 val brUpdate = new BranchUpdateInfo 181 val debug = new DebugBundle 182} 183 184class ExuIO extends XSBundle { 185 val in = Flipped(DecoupledIO(new ExuInput)) 186 val redirect = Flipped(ValidIO(new Redirect)) 187 val out = DecoupledIO(new ExuOutput) 188 // for csr 189 val exception = Flipped(ValidIO(new MicroOp)) 190 // for Lsu 191 val dmem = new SimpleBusUC 192 val mcommit = Input(UInt(3.W)) 193} 194 195class RoqCommit extends XSBundle { 196 val uop = new MicroOp 197 val isWalk = Bool() 198} 199 200class FrontendToBackendIO extends XSBundle { 201 // to backend end 202 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 203 // from backend 204 val redirect = Flipped(ValidIO(new Redirect)) 205 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 206 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 207} 208