1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{ICache, DCache, L1plusCache, DCacheParameters, ICacheParameters, L1plusCacheParameters, PTW, Uncache} 14import chipsalliance.rocketchip.config 15import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, AddressSet} 16import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar, TLWidthWidget, TLFilter, TLToAXI4} 17import freechips.rocketchip.devices.tilelink.{TLError, DevNullParams} 18import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 19import freechips.rocketchip.amba.axi4.{AXI4ToTL, AXI4IdentityNode, AXI4UserYanker, AXI4Fragmenter, AXI4IdIndexer, AXI4Deinterleaver} 20import utils._ 21 22case class XSCoreParameters 23( 24 XLEN: Int = 64, 25 HasMExtension: Boolean = true, 26 HasCExtension: Boolean = true, 27 HasDiv: Boolean = true, 28 HasICache: Boolean = true, 29 HasDCache: Boolean = true, 30 EnableStoreQueue: Boolean = true, 31 AddrBits: Int = 64, 32 VAddrBits: Int = 39, 33 PAddrBits: Int = 40, 34 HasFPU: Boolean = true, 35 FectchWidth: Int = 8, 36 EnableBPU: Boolean = true, 37 EnableBPD: Boolean = true, 38 EnableRAS: Boolean = true, 39 EnableLB: Boolean = true, 40 EnableLoop: Boolean = true, 41 EnableSC: Boolean = false, 42 HistoryLength: Int = 64, 43 BtbSize: Int = 2048, 44 JbtacSize: Int = 1024, 45 JbtacBanks: Int = 8, 46 RasSize: Int = 16, 47 CacheLineSize: Int = 512, 48 UBtbWays: Int = 16, 49 BtbWays: Int = 2, 50 IBufSize: Int = 64, 51 DecodeWidth: Int = 6, 52 RenameWidth: Int = 6, 53 CommitWidth: Int = 6, 54 BrqSize: Int = 32, 55 IssQueSize: Int = 8, 56 NRPhyRegs: Int = 160, 57 NRIntReadPorts: Int = 14, 58 NRIntWritePorts: Int = 8, 59 NRFpReadPorts: Int = 14, 60 NRFpWritePorts: Int = 8, 61 LoadQueueSize: Int = 64, 62 StoreQueueSize: Int = 48, 63 RoqSize: Int = 192, 64 dpParams: DispatchParameters = DispatchParameters( 65 DqEnqWidth = 4, 66 IntDqSize = 128, 67 FpDqSize = 128, 68 LsDqSize = 96, 69 IntDqDeqWidth = 4, 70 FpDqDeqWidth = 4, 71 LsDqDeqWidth = 4, 72 IntDqReplayWidth = 4, 73 FpDqReplayWidth = 4, 74 LsDqReplayWidth = 4 75 ), 76 exuParameters: ExuParameters = ExuParameters( 77 JmpCnt = 1, 78 AluCnt = 4, 79 MulCnt = 0, 80 MduCnt = 2, 81 FmacCnt = 4, 82 FmiscCnt = 2, 83 FmiscDivSqrtCnt = 0, 84 LduCnt = 2, 85 StuCnt = 2 86 ), 87 LoadPipelineWidth: Int = 2, 88 StorePipelineWidth: Int = 2, 89 StoreBufferSize: Int = 16, 90 RefillSize: Int = 512, 91 TlbEntrySize: Int = 32, 92 TlbL2EntrySize: Int = 256, // or 512 93 PtwL1EntrySize: Int = 16, 94 PtwL2EntrySize: Int = 256, 95 NumPerfCounters: Int = 16 96) 97 98trait HasXSParameter { 99 100 val core = Parameters.get.coreParameters 101 val env = Parameters.get.envParameters 102 103 val XLEN = core.XLEN 104 val HasMExtension = core.HasMExtension 105 val HasCExtension = core.HasCExtension 106 val HasDiv = core.HasDiv 107 val HasIcache = core.HasICache 108 val HasDcache = core.HasDCache 109 val EnableStoreQueue = core.EnableStoreQueue 110 val AddrBits = core.AddrBits // AddrBits is used in some cases 111 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 112 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 113 val AddrBytes = AddrBits / 8 // unused 114 val DataBits = XLEN 115 val DataBytes = DataBits / 8 116 val HasFPU = core.HasFPU 117 val FetchWidth = core.FectchWidth 118 val PredictWidth = FetchWidth * 2 119 val EnableBPU = core.EnableBPU 120 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 121 val EnableRAS = core.EnableRAS 122 val EnableLB = core.EnableLB 123 val EnableLoop = core.EnableLoop 124 val EnableSC = core.EnableSC 125 val HistoryLength = core.HistoryLength 126 val BtbSize = core.BtbSize 127 // val BtbWays = 4 128 val BtbBanks = PredictWidth 129 // val BtbSets = BtbSize / BtbWays 130 val JbtacSize = core.JbtacSize 131 val JbtacBanks = core.JbtacBanks 132 val RasSize = core.RasSize 133 val CacheLineSize = core.CacheLineSize 134 val CacheLineHalfWord = CacheLineSize / 16 135 val ExtHistoryLength = HistoryLength + 64 136 val UBtbWays = core.UBtbWays 137 val BtbWays = core.BtbWays 138 val IBufSize = core.IBufSize 139 val DecodeWidth = core.DecodeWidth 140 val RenameWidth = core.RenameWidth 141 val CommitWidth = core.CommitWidth 142 val BrqSize = core.BrqSize 143 val IssQueSize = core.IssQueSize 144 val BrTagWidth = log2Up(BrqSize) 145 val NRPhyRegs = core.NRPhyRegs 146 val PhyRegIdxWidth = log2Up(NRPhyRegs) 147 val RoqSize = core.RoqSize 148 val LoadQueueSize = core.LoadQueueSize 149 val StoreQueueSize = core.StoreQueueSize 150 val dpParams = core.dpParams 151 val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth 152 val exuParameters = core.exuParameters 153 val NRIntReadPorts = core.NRIntReadPorts 154 val NRIntWritePorts = core.NRIntWritePorts 155 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 156 val NRFpReadPorts = core.NRFpReadPorts 157 val NRFpWritePorts = core.NRFpWritePorts 158 val LoadPipelineWidth = core.LoadPipelineWidth 159 val StorePipelineWidth = core.StorePipelineWidth 160 val StoreBufferSize = core.StoreBufferSize 161 val RefillSize = core.RefillSize 162 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 163 val TlbEntrySize = core.TlbEntrySize 164 val TlbL2EntrySize = core.TlbL2EntrySize 165 val PtwL1EntrySize = core.PtwL1EntrySize 166 val PtwL2EntrySize = core.PtwL2EntrySize 167 val NumPerfCounters = core.NumPerfCounters 168 169 val icacheParameters = ICacheParameters( 170 nMissEntries = 2 171 ) 172 173 val l1plusCacheParameters = L1plusCacheParameters( 174 tagECC = Some("secded"), 175 dataECC = Some("secded"), 176 nMissEntries = 8 177 ) 178 179 val dcacheParameters = DCacheParameters( 180 tagECC = Some("secded"), 181 dataECC = Some("secded"), 182 nMissEntries = 16, 183 nLoadMissEntries = 8, 184 nStoreMissEntries = 8 185 ) 186 187 val LRSCCycles = 100 188 189 190 // cache hierarchy configurations 191 val l1BusDataWidth = 256 192 193 // L2 configurations 194 val L1BusWidth = 256 195 val L2Size = 512 * 1024 // 512KB 196 val L2BlockSize = 64 197 val L2NWays = 8 198 val L2NSets = L2Size / L2BlockSize / L2NWays 199 200 // L3 configurations 201 val L2BusWidth = 256 202 val L3Size = 4 * 1024 * 1024 // 4MB 203 val L3BlockSize = 64 204 val L3NBanks = 4 205 val L3NWays = 8 206 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 207 208 // on chip network configurations 209 val L3BusWidth = 256 210} 211 212trait HasXSLog { this: RawModule => 213 implicit val moduleName: String = this.name 214} 215 216abstract class XSModule extends MultiIOModule 217 with HasXSParameter 218 with HasExceptionNO 219 with HasXSLog 220{ 221 def io: Record 222} 223 224//remove this trait after impl module logic 225trait NeedImpl { this: RawModule => 226 override protected def IO[T <: Data](iodef: T): T = { 227 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 228 val io = chisel3.experimental.IO(iodef) 229 io <> DontCare 230 io 231 } 232} 233 234abstract class XSBundle extends Bundle 235 with HasXSParameter 236 237case class EnviromentParameters 238( 239 FPGAPlatform: Boolean = true, 240 EnableDebug: Boolean = false 241) 242 243object AddressSpace extends HasXSParameter { 244 // (start, size) 245 // address out of MMIO will be considered as DRAM 246 def mmio = List( 247 (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 248 (0x40000000L, 0x40000000L) // external devices 249 ) 250 251 def isMMIO(addr: UInt): Bool = mmio.map(range => { 252 require(isPow2(range._2)) 253 val bits = log2Up(range._2) 254 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 255 }).reduce(_ || _) 256} 257 258 259 260class XSCore()(implicit p: config.Parameters) extends LazyModule with HasXSParameter { 261 262 // inner nodes 263 val dcache = LazyModule(new DCache()) 264 val uncache = LazyModule(new Uncache()) 265 val l1pluscache = LazyModule(new L1plusCache()) 266 val ptw = LazyModule(new PTW()) 267 268 // out facing nodes 269 val mem = TLIdentityNode() 270 val mmio = uncache.clientNode 271 272 // L1 to L2 network 273 // ------------------------------------------------- 274 private val l2_xbar = TLXbar() 275 276 private val l2 = LazyModule(new InclusiveCache( 277 CacheParameters( 278 level = 2, 279 ways = L2NWays, 280 sets = L2NSets, 281 blockBytes = L2BlockSize, 282 beatBytes = L1BusWidth / 8, // beatBytes = l1BusDataWidth / 8 283 cacheName = s"L2" 284 ), 285 InclusiveCacheMicroParameters( 286 writeBytes = 8 287 ) 288 )) 289 290 l2_xbar := TLBuffer() := DebugIdentityNode() := dcache.clientNode 291 l2_xbar := TLBuffer() := DebugIdentityNode() := l1pluscache.clientNode 292 l2_xbar := TLBuffer() := DebugIdentityNode() := ptw.node 293 l2.node := TLBuffer() := DebugIdentityNode() := l2_xbar 294 295 mem := l2.node 296 297 lazy val module = new XSCoreImp(this) 298} 299 300class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 301 with HasXSParameter 302 with HasExeBlockHelper 303{ 304 val io = IO(new Bundle { 305 val externalInterrupt = new ExternalInterruptIO 306 }) 307 308 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 309 310 // to fast wake up fp, mem rs 311 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 312 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 313 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 314 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 315 316 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 317 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 318 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 319 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 320 321 val frontend = Module(new Frontend) 322 val ctrlBlock = Module(new CtrlBlock) 323 val integerBlock = Module(new IntegerBlock( 324 fastWakeUpIn = fpBlockFastWakeUpInt, 325 slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs, 326 fastFpOut = intBlockFastWakeUpFp, 327 slowFpOut = intBlockSlowWakeUpFp, 328 fastIntOut = intBlockFastWakeUpInt, 329 slowIntOut = intBlockSlowWakeUpInt 330 )) 331 val floatBlock = Module(new FloatBlock( 332 fastWakeUpIn = intBlockFastWakeUpFp, 333 slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs, 334 fastFpOut = fpBlockFastWakeUpFp, 335 slowFpOut = fpBlockSlowWakeUpFp, 336 fastIntOut = fpBlockFastWakeUpInt, 337 slowIntOut = fpBlockSlowWakeUpInt 338 )) 339 val memBlock = Module(new MemBlock( 340 fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp, 341 slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp, 342 fastFpOut = Seq(), 343 slowFpOut = loadExuConfigs, 344 fastIntOut = Seq(), 345 slowIntOut = loadExuConfigs 346 )) 347 348 val dcache = outer.dcache.module 349 val uncache = outer.uncache.module 350 val l1pluscache = outer.l1pluscache.module 351 val ptw = outer.ptw.module 352 val icache = Module(new ICache) 353 354 frontend.io.backend <> ctrlBlock.io.frontend 355 frontend.io.icacheResp <> icache.io.resp 356 frontend.io.icacheToTlb <> icache.io.tlb 357 icache.io.req <> frontend.io.icacheReq 358 icache.io.flush <> frontend.io.icacheFlush 359 frontend.io.sfence <> integerBlock.io.fenceio.sfence 360 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 361 362 icache.io.mem_acquire <> l1pluscache.io.req 363 l1pluscache.io.resp <> icache.io.mem_grant 364 l1pluscache.io.flush := icache.io.l1plusflush 365 icache.io.fencei := integerBlock.io.fenceio.fencei 366 367 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 368 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 369 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 370 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 371 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 372 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 373 374 integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops 375 integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast 376 integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow 377 378 floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops 379 floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast 380 floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow 381 382 383 integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B) 384 integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B) 385 floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B) 386 floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B) 387 388 val wakeUpMem = Seq( 389 integerBlock.io.wakeUpIntOut, 390 integerBlock.io.wakeUpFpOut, 391 floatBlock.io.wakeUpIntOut, 392 floatBlock.io.wakeUpFpOut 393 ) 394 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 395 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => { 396 val raw = WireInit(f) 397 raw 398 })) 399 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => { 400 val raw = WireInit(s) 401 raw 402 })) 403 404 integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags 405 integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 406 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 407 integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt 408 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 409 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 410 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 411 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 412 integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr 413 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 414 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 415 416 floatBlock.io.frm <> integerBlock.io.csrio.frm 417 418 memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits 419 memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr 420 memBlock.io.lsqio.oldestStore <> ctrlBlock.io.oldestStore 421 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx 422 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx 423 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType) 424 425 ptw.io.tlb(0) <> memBlock.io.ptw 426 ptw.io.tlb(1) <> frontend.io.ptw 427 ptw.io.sfence <> integerBlock.io.fenceio.sfence 428 ptw.io.csr <> integerBlock.io.csrio.tlb 429 430 dcache.io.lsu.load <> memBlock.io.dcache.loadUnitToDcacheVec 431 dcache.io.lsu.lsq <> memBlock.io.dcache.loadMiss 432 dcache.io.lsu.atomics <> memBlock.io.dcache.atomics 433 dcache.io.lsu.store <> memBlock.io.dcache.sbufferToDcache 434 uncache.io.lsq <> memBlock.io.dcache.uncache 435 436 if (!env.FPGAPlatform) { 437 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 438 ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug) 439 ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug) 440 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 441 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 442 } 443 444} 445