1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{PipelineConnect, ZeroExt} 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 10import xiangshan.backend.ctrlblock.CtrlBlock 11import xiangshan.backend.datapath.WbConfig._ 12import xiangshan.backend.datapath.{DataPath, NewPipelineConnect, WbDataPath} 13import xiangshan.backend.exu.ExuBlock 14import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 15import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, PerfCounterIO, FuConfig} 16import xiangshan.backend.issue.{Scheduler, IntScheduler, MemScheduler, VfScheduler} 17import xiangshan.backend.rob.RobLsqIO 18import xiangshan.frontend.{FtqPtr, FtqRead} 19import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 20 21class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 22 with HasXSParameter { 23 24 println("[Backend] ExuConfigs:") 25 for (exuCfg <- params.allExuParams) { 26 val fuConfigs = exuCfg.fuConfigs 27 val wbPortConfigs = exuCfg.wbPortConfigs 28 val immType = exuCfg.immType 29 println("[Backend] " + 30 s"${exuCfg.name}: " + 31 s"${ fuConfigs.map(_.name).mkString("fu(s): {", ",", "}") }, " + 32 s"${ wbPortConfigs.mkString("wb: {", ",", "}") }, " + 33 s"${ immType.map(SelImm.mkString(_)).mkString("imm: {", "," , "}") }") 34 require(wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 35 fuConfigs.map(_.writeIntRf).reduce(_ || _), 36 "int wb port has no priority" ) 37 require(wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 38 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 39 "vec wb port has no priority" ) 40 } 41 42 for (cfg <- FuConfig.allConfigs) { 43 println(s"[Backend] $cfg") 44 } 45 46 val ctrlBlock = LazyModule(new CtrlBlock(params)) 47 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 48 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 49 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 50 val dataPath = LazyModule(new DataPath(params)) 51 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 52 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 53 54 lazy val module = new BackendImp(this) 55} 56 57class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 58 with HasXSParameter{ 59 implicit private val params = wrapper.params 60 val io = IO(new BackendIO()(p, wrapper.params)) 61 62 private val ctrlBlock = wrapper.ctrlBlock.module 63 private val intScheduler = wrapper.intScheduler.get.module 64 private val vfScheduler = wrapper.vfScheduler.get.module 65 private val memScheduler = wrapper.memScheduler.get.module 66 private val dataPath = wrapper.dataPath.module 67 private val intExuBlock = wrapper.intExuBlock.get.module 68 private val vfExuBlock = wrapper.vfExuBlock.get.module 69 private val wbDataPath = Module(new WbDataPath(params)) 70 71 private val (intRespWrite, vfRespWrite, memRespWrite) = (intScheduler.io.toWbFuBusyTable.intFuBusyTableWrite, 72 vfScheduler.io.toWbFuBusyTable.intFuBusyTableWrite, 73 memScheduler.io.toWbFuBusyTable.intFuBusyTableWrite) 74 private val (intRespRead, vfRespRead, memRespRead) = (intScheduler.io.fromWbFuBusyTable.fuBusyTableRead, 75 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead, 76 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead) 77 private val intAllRespWrite = (intRespWrite ++ vfRespWrite ++ memRespWrite).flatten 78 private val intAllRespRead = (intRespRead ++ vfRespRead ++ memRespRead).flatten.map(_.intWbBusyTable) 79 private val intAllWbConflictFlag = dataPath.io.wbConfictRead.flatten.flatten.map(_.intConflict) 80 81 private val (vfIntRespWrite, vfVfRespWrite, vfMemRespWrite) = (intScheduler.io.toWbFuBusyTable.vfFuBusyTableWrite, 82 vfScheduler.io.toWbFuBusyTable.vfFuBusyTableWrite, 83 memScheduler.io.toWbFuBusyTable.vfFuBusyTableWrite) 84 85 private val vfAllRespWrite = (vfIntRespWrite ++ vfVfRespWrite ++ vfMemRespWrite).flatten 86 private val vfAllRespRead = (intRespRead ++ vfRespRead ++ memRespRead).flatten.map(_.vfWbBusyTable) 87 private val vfAllWbConflictFlag = dataPath.io.wbConfictRead.flatten.flatten.map(_.vfConflict) 88 89 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 90 private val allExuParams = params.allExuParams 91 private val intRespWriteWithParams = intAllRespWrite.zip(allExuParams) 92 println(s"[intRespWriteWithParams] is ${intRespWriteWithParams}") 93 intRespWriteWithParams.foreach{ case(l,r) => 94 println(s"FuBusyTableWriteBundle is ${l}, ExeUnitParams is ${r}") 95 } 96 private val vfRespWriteWithParams = vfAllRespWrite.zip(allExuParams) 97 98 private val intWBAllFuGroup = params.getIntWBExeGroup.map{ case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs)) } 99 private val intWBFuGroup = params.getIntWBExeGroup.map{ case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs).filter(_.writeIntRf)) } 100 private val intLatencyCertains = intWBAllFuGroup.map{case (k,v) => (k, v.map(_.latency.latencyVal.nonEmpty).reduce(_ && _))} 101 private val intWBFuLatencyMap = intLatencyCertains.map{case (k, latencyCertain) => 102 if (latencyCertain) Some(intWBFuGroup(k).map(y => (y.fuType, y.latency.latencyVal.get))) 103 else None 104 }.toSeq 105 private val intWBFuLatencyValMax = intWBFuLatencyMap.map(latencyMap=> latencyMap.map(x => x.map(_._2).max)) 106 107 private val vfWBAllFuGroup = params.getVfWBExeGroup.map{ case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs)) } 108 private val vfWBFuGroup = params.getVfWBExeGroup.map{ case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs).filter(x => x.writeFpRf || x.writeVecRf)) } 109 private val vfLatencyCertains = vfWBAllFuGroup.map{case (k,v) => (k, v.map(_.latency.latencyVal.nonEmpty).reduce(_ && _))} 110 val vfWBFuLatencyMap = vfLatencyCertains.map { case (k, latencyCertain) => 111 if (latencyCertain) Some(vfWBFuGroup(k).map(y => (y.fuType, y.latency.latencyVal.get))) 112 else None 113 }.toSeq 114 private val vfWBFuLatencyValMax = vfWBFuLatencyMap.map(latencyMap => latencyMap.map(x => x.map(_._2).max)) 115 116 private val intWBFuBusyTable = intWBFuLatencyValMax.map { case y => if (y.getOrElse(0)>0) Some(Reg(UInt(y.getOrElse(1).W))) else None } 117 println(s"[intWBFuBusyTable] is ${intWBFuBusyTable.map(x => x) }") 118 private val vfWBFuBusyTable = vfWBFuLatencyValMax.map { case y => if (y.getOrElse(0)>0) Some(Reg(UInt(y.getOrElse(1).W))) else None } 119 println(s"[vfWBFuBusyTable] is ${vfWBFuBusyTable.map(x => x) }") 120 121 private val intWBPortConflictFlag = intWBFuLatencyValMax.map { case y => if (y.getOrElse(0) > 0) Some(Reg(Bool())) else None } 122 private val vfWBPortConflictFlag = vfWBFuLatencyValMax.map { case y => if (y.getOrElse(0) > 0) Some(Reg(Bool())) else None } 123 124 intWBPortConflictFlag.foreach(x => if(x.isDefined) dontTouch((x.get))) 125 vfWBPortConflictFlag.foreach(x => if(x.isDefined) dontTouch((x.get))) 126 127 128 intWBFuBusyTable.map(x => x.map(dontTouch(_))) 129 vfWBFuBusyTable.map(x => x.map(dontTouch(_))) 130 131 132 private val intWBFuBusyTableWithPort = intWBFuBusyTable.zip(intWBFuGroup.map(_._1)) 133 private val intWBPortConflictFlagWithPort = intWBPortConflictFlag.zip(intWBFuGroup.map(_._1)) 134 // intWBFuBusyTable write 135 intWBFuBusyTableWithPort.zip(intWBPortConflictFlag).zip(intWBFuLatencyValMax).foreach { 136 case (((busyTable, wbPort), wbPortConflictFlag), maxLatency) => 137 if (busyTable.nonEmpty) { 138 val maskWidth = maxLatency.getOrElse(0) 139 val defaultMask = ((1 << maskWidth) - 1).U 140 val deqWbFuBusyTableValue = intRespWriteWithParams.zipWithIndex.filter { case ((r, p), idx) => 141 (p.wbPortConfigs.collectFirst{ case x: IntWB => x.port }.getOrElse(-1)) == wbPort 142 }.map{case ((r, p), idx) => 143 val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp) 144 Mux(resps(0).valid && resps(0).bits.respType === RSFeedbackType.issueSuccess, 145 VecInit((0 until maxLatency.getOrElse(0) + 1).map { case latency => 146 val latencyNumFuType = p.writeIntFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == latency).map(_.fuType) 147 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(0).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num 148 isLatencyNum 149 }).asUInt, 150 0.U) 151 } 152// deqWbFuBusyTableValue.foreach(x => dontTouch(x)) 153 val deqIsLatencyNumMask = (deqWbFuBusyTableValue.reduce(_ | _) >> 1).asUInt 154 wbPortConflictFlag.get := deqWbFuBusyTableValue.reduce(_ & _).orR 155 156 val og0IsLatencyNumMask = WireInit(defaultMask) 157 og0IsLatencyNumMask := intRespWriteWithParams.zipWithIndex.map { case ((r, p), idx) => 158 val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp) 159 val matchI = (p.wbPortConfigs.collectFirst { case x: IntWB => x.port }.getOrElse(-1)) == wbPort 160 if (matchI) { 161 Mux(resps(1).valid && resps(1).bits.respType === RSFeedbackType.rfArbitFail, 162 (~(Cat(VecInit((0 until maxLatency.getOrElse(0)).map { case num => 163 val latencyNumFuType = p.writeIntFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType) 164 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(1).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num 165 isLatencyNum 166 }).asUInt, 0.U(1.W)))).asUInt, 167 defaultMask) 168 } else defaultMask 169 }.reduce(_&_) 170 val og1IsLatencyNumMask = WireInit(defaultMask) 171 og1IsLatencyNumMask := intRespWriteWithParams.zipWithIndex.map { case ((r, p), idx) => 172 val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp) 173 val matchI = (p.wbPortConfigs.collectFirst { case x: IntWB => x.port }.getOrElse(-1)) == wbPort 174 if (matchI && resps.length==3) { 175 Mux(resps(2).valid && resps(2).bits.respType === RSFeedbackType.fuBusy, 176 (~(Cat(VecInit((0 until maxLatency.getOrElse(0)).map { case num => 177 val latencyNumFuType = p.writeIntFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType) 178 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(2).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num 179 isLatencyNum 180 }).asUInt, 0.U(2.W)))).asUInt, 181 defaultMask) 182 } else defaultMask 183 }.reduce(_ & _) 184 dontTouch(deqIsLatencyNumMask) 185 dontTouch(og0IsLatencyNumMask) 186 dontTouch(og1IsLatencyNumMask) 187 busyTable.get := ((busyTable.get >> 1.U).asUInt() | deqIsLatencyNumMask) & og0IsLatencyNumMask.asUInt() & og1IsLatencyNumMask.asUInt() 188 } 189 } 190 // intWBFuBusyTable read 191 for(i <- 0 until intAllRespRead.size){ 192 if(intAllRespRead(i).isDefined){ 193 intAllRespRead(i).get := intWBFuBusyTableWithPort.map { case (busyTable, wbPort) => 194 val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: IntWB => x.port }.getOrElse(-1)) == wbPort 195 if (busyTable.nonEmpty && matchI) { 196 busyTable.get.asTypeOf(intAllRespRead(i).get) 197 } else { 198 0.U.asTypeOf(intAllRespRead(i).get) 199 } 200 }.reduce(_ | _) 201 } 202 203 if (intAllWbConflictFlag(i).isDefined) { 204 intAllWbConflictFlag(i).get := intWBPortConflictFlagWithPort.map { case (conflictFlag, wbPort) => 205 val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: IntWB => x.port }.getOrElse(-1)) == wbPort 206 if (conflictFlag.nonEmpty && matchI) { 207 conflictFlag.get 208 } else false.B 209 }.reduce(_ | _) 210 } 211 } 212 213 private val vfWBFuBusyTableWithPort = vfWBFuBusyTable.zip(vfWBFuGroup.map(_._1)) 214 private val vfWBPortConflictFlagWithPort = vfWBPortConflictFlag.zip(vfWBFuGroup.map(_._1)) 215 // vfWBFuBusyTable write 216 vfWBFuBusyTableWithPort.zip(vfWBPortConflictFlag).zip(vfWBFuLatencyValMax).foreach{ 217 case(((busyTable, wbPort), wbPortConflictFlag), maxLatency) => 218 if(busyTable.nonEmpty){ 219 val maskWidth = maxLatency.getOrElse(0) 220 val defaultMask = ((1 << maskWidth) - 1).U 221 val deqWbFuBusyTableValue = vfRespWriteWithParams.zipWithIndex.filter { case ((_, p), _) => 222 (p.wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort 223 }.map { case ((r, p), _) => 224 val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp) 225 Mux(resps(0).valid && resps(0).bits.respType === RSFeedbackType.issueSuccess, 226 VecInit((0 until maxLatency.getOrElse(0) + 1).map { case latency => 227 val latencyNumFuType = p.writeVfFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == latency).map(_.fuType) 228 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(0).bits.fuType === futype.U)).asUInt.orR // The latency of the deqResp inst is Num 229 isLatencyNum 230 }).asUInt, 231 0.U) 232 } 233 val deqIsLatencyNumMask = (deqWbFuBusyTableValue.reduce(_ | _) >> 1).asUInt 234 wbPortConflictFlag.get := deqWbFuBusyTableValue.reduce(_ & _).orR 235 236 val og0IsLatencyNumMask = WireInit(defaultMask) 237 og0IsLatencyNumMask := vfRespWriteWithParams.zipWithIndex.map { case ((r, p), idx) => 238 val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp) 239 val matchI = (p.wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort 240 if (matchI) { 241 Mux(resps(1).valid && resps(1).bits.respType === RSFeedbackType.rfArbitFail, 242 (~(Cat(VecInit((0 until maxLatency.getOrElse(0)).map { case num => 243 val latencyNumFuType = p.writeVfFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType) 244 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(1).bits.fuType === futype.U)).asUInt.orR // The latency of the deqResp inst is Num 245 isLatencyNum 246 }).asUInt, 0.U(1.W)))).asUInt, 247 defaultMask) 248 } else defaultMask 249 }.reduce(_ & _) 250 val og1IsLatencyNumMask = WireInit(defaultMask) 251 og1IsLatencyNumMask := vfRespWriteWithParams.zipWithIndex.map { case ((r, p), idx) => 252 val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp) 253 254 val matchI = (p.wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort 255 if (matchI && resps.length == 3) { 256 Mux(resps(2).valid && resps(2).bits.respType === RSFeedbackType.fuBusy, 257 (~(Cat(VecInit((0 until maxLatency.getOrElse(0)).map { case num => 258 val latencyNumFuType = p.writeVfFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType) 259 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(2).bits.fuType === futype.U)).asUInt.orR // The latency of the deqResp inst is Num 260 isLatencyNum 261 }).asUInt, 0.U(2.W)))).asUInt, 262 defaultMask) 263 } else defaultMask 264 }.reduce(_ & _) 265 dontTouch(deqIsLatencyNumMask) 266 dontTouch(og0IsLatencyNumMask) 267 dontTouch(og1IsLatencyNumMask) 268 busyTable.get := ((busyTable.get >> 1.U).asUInt | deqIsLatencyNumMask) & og0IsLatencyNumMask.asUInt & og1IsLatencyNumMask.asUInt 269 } 270 } 271 272 // vfWBFuBusyTable read 273 for (i <- 0 until vfAllRespRead.size) { 274 if(vfAllRespRead(i).isDefined){ 275 vfAllRespRead(i).get := vfWBFuBusyTableWithPort.map { case (busyTable, wbPort) => 276 val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort 277 if (busyTable.nonEmpty && matchI) { 278 busyTable.get.asTypeOf(vfAllRespRead(i).get) 279 } else { 280 0.U.asTypeOf(vfAllRespRead(i).get) 281 } 282 }.reduce(_ | _) 283 } 284 285 if(vfAllWbConflictFlag(i).isDefined){ 286 vfAllWbConflictFlag(i).get := vfWBPortConflictFlagWithPort.map { case (conflictFlag, wbPort) => 287 val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort 288 if (conflictFlag.nonEmpty && matchI) { 289 conflictFlag.get 290 } else false.B 291 }.reduce(_ | _) 292 } 293 } 294 295 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 296 ctrlBlock.io.frontend <> io.frontend 297 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 298 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 299 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 300 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 301 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 302 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 303 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 304 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 305 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 306 307 intScheduler.io.fromTop.hartId := io.fromTop.hartId 308 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 309 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 310 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 311 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 312 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 313 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 314 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 315 316 memScheduler.io.fromTop.hartId := io.fromTop.hartId 317 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 318 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 319 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 320 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 321 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 322 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 323 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 324 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 325 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 326 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 327 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 328 sink.valid := source.valid 329 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 330 sink.bits.uop.robIdx := source.bits.robIdx 331 } 332 io.mem.ldaIqFeedback <> memScheduler.io.fromMem.get.ldaFeedback 333 io.mem.staIqFeedback <> memScheduler.io.fromMem.get.staFeedback 334 335 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 336 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 337 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 338 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 339 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 340 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 341 342 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 343 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 344 val vconfig = dataPath.io.vconfigReadPort.data 345 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 346 for (i <- 0 until dataPath.io.fromIntIQ.length) { 347 for (j <- 0 until dataPath.io.fromIntIQ(i).length) { 348 NewPipelineConnect(intScheduler.io.toDataPath(i)(j), dataPath.io.fromIntIQ(i)(j), dataPath.io.fromIntIQ(i)(j).valid, 349 intScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("intScheduler2DataPathPipe")) 350 intScheduler.io.fromDataPath(i)(j) := dataPath.io.toIntIQ(i)(j) 351 } 352 } 353 354 for (i <- 0 until dataPath.io.fromVfIQ.length) { 355 for (j <- 0 until dataPath.io.fromVfIQ(i).length) { 356 NewPipelineConnect(vfScheduler.io.toDataPath(i)(j), dataPath.io.fromVfIQ(i)(j), dataPath.io.fromVfIQ(i)(j).valid, 357 vfScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("vfScheduler2DataPathPipe")) 358 vfScheduler.io.fromDataPath(i)(j) := dataPath.io.toVfIQ(i)(j) 359 } 360 } 361 362 for (i <- 0 until dataPath.io.fromMemIQ.length) { 363 for (j <- 0 until dataPath.io.fromMemIQ(i).length) { 364 NewPipelineConnect(memScheduler.io.toDataPath(i)(j), dataPath.io.fromMemIQ(i)(j), dataPath.io.fromMemIQ(i)(j).valid, 365 memScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("memScheduler2DataPathPipe")) 366 memScheduler.io.fromDataPath(i)(j) := dataPath.io.toMemIQ(i)(j) 367 } 368 } 369 370 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 371 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 372 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 373 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 374 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 375 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 376 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 377 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 378 379 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 380 for (i <- 0 until intExuBlock.io.in.length) { 381 for (j <- 0 until intExuBlock.io.in(i).length) { 382 NewPipelineConnect(dataPath.io.toIntExu(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 383 Mux(dataPath.io.toIntExu(i)(j).fire, 384 dataPath.io.toIntExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 385 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 386 } 387 } 388 389 private val csrio = intExuBlock.io.csrio.get 390 csrio.hartId := io.fromTop.hartId 391 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 392 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 393 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 394 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 395 csrio.fpu.isIllegal := false.B // Todo: remove it 396 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 397 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 398 399 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 400 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 401 val debugVl = debugVconfig.vl 402 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 403 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 404 csrio.vpu.set_vstart.bits := 0.U 405 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 406 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 407 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 408 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 409 csrio.exception := ctrlBlock.io.robio.exception 410 csrio.memExceptionVAddr := io.mem.exceptionVAddr 411 csrio.externalInterrupt := io.fromTop.externalInterrupt 412 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 413 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 414 csrio.perf <> io.perf 415 private val fenceio = intExuBlock.io.fenceio.get 416 fenceio.disableSfence := csrio.disableSfence 417 io.fenceio <> fenceio 418 419 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 420 for (i <- 0 until vfExuBlock.io.in.size) { 421 for (j <- 0 until vfExuBlock.io.in(i).size) { 422 NewPipelineConnect(dataPath.io.toFpExu(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 423 Mux(dataPath.io.toFpExu(i)(j).fire, 424 dataPath.io.toFpExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 425 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 426 } 427 } 428 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 429 430 wbDataPath.io.flush := ctrlBlock.io.redirect 431 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 432 wbDataPath.io.fromIntExu <> intExuBlock.io.out 433 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 434 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 435 sink.valid := source.valid 436 source.ready := sink.ready 437 sink.bits.data := source.bits.data 438 sink.bits.pdest := source.bits.uop.pdest 439 sink.bits.robIdx := source.bits.uop.robIdx 440 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 441 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 442 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 443 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 444 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 445 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 446 sink.bits.debug := source.bits.debug 447 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 448 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 449 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 450 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 451 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 452 } 453 454 // to mem 455 io.mem.redirect := ctrlBlock.io.redirect 456 io.mem.issueUops.zip(dataPath.io.toMemExu.flatten).foreach { case (sink, source) => 457 sink.valid := source.valid 458 source.ready := sink.ready 459 sink.bits.iqIdx := source.bits.iqIdx 460 sink.bits.isFirstIssue := source.bits.isFirstIssue 461 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 462 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 463 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 464 sink.bits.uop.fuType := source.bits.fuType 465 sink.bits.uop.fuOpType := source.bits.fuOpType 466 sink.bits.uop.imm := source.bits.imm 467 sink.bits.uop.robIdx := source.bits.robIdx 468 sink.bits.uop.pdest := source.bits.pdest 469 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 470 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 471 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 472 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 473 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 474 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 475 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 476 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 477 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 478 } 479 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 480 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 481 io.mem.tlbCsr := csrio.tlb 482 io.mem.csrCtrl := csrio.customCtrl 483 io.mem.sfence := fenceio.sfence 484 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 485 require(io.mem.loadPcRead.size == params.LduCnt) 486 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 487 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 488 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 489 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 490 } 491 // mem io 492 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 493 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 494 io.mem.toSbuffer <> fenceio.sbuffer 495 496 io.frontendSfence := fenceio.sfence 497 io.frontendTlbCsr := csrio.tlb 498 io.frontendCsrCtrl := csrio.customCtrl 499 500 io.tlb <> csrio.tlb 501 502 io.csrCustomCtrl := csrio.customCtrl 503 504 dontTouch(memScheduler.io) 505 dontTouch(io.mem) 506 dontTouch(dataPath.io.toMemExu) 507 dontTouch(wbDataPath.io.fromMemExu) 508} 509 510class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 511 // params alias 512 private val LoadQueueSize = VirtualLoadQueueSize 513 // In/Out // Todo: split it into one-direction bundle 514 val lsqEnqIO = Flipped(new LsqEnqIO) 515 val robLsqIO = new RobLsqIO 516 val toSbuffer = new FenceToSbuffer 517 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 518 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 519 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 520 521 // Input 522 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 523 524 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 525 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 526 val memoryViolation = Flipped(ValidIO(new Redirect)) 527 val exceptionVAddr = Input(UInt(VAddrBits.W)) 528 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 529 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 530 531 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 532 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 533 534 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 535 val stIssuePtr = Input(new SqPtr()) 536 537 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 538 539 // Output 540 val redirect = ValidIO(new Redirect) // rob flush MemBlock 541 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 542 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 543 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 544 545 val tlbCsr = Output(new TlbCsrBundle) 546 val csrCtrl = Output(new CustomCSRCtrlIO) 547 val sfence = Output(new SfenceBundle) 548 val isStoreException = Output(Bool()) 549} 550 551class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 552 val fromTop = new Bundle { 553 val hartId = Input(UInt(8.W)) 554 val externalInterrupt = new ExternalInterruptIO 555 } 556 557 val toTop = new Bundle { 558 val cpuHalted = Output(Bool()) 559 } 560 561 val fenceio = new FenceIO 562 // Todo: merge these bundles into BackendFrontendIO 563 val frontend = Flipped(new FrontendToCtrlIO) 564 val frontendSfence = Output(new SfenceBundle) 565 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 566 val frontendTlbCsr = Output(new TlbCsrBundle) 567 // distributed csr write 568 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 569 570 val mem = new BackendMemIO 571 572 val perf = Input(new PerfCounterIO) 573 574 val tlb = Output(new TlbCsrBundle) 575 576 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 577} 578