refactor(DFT): refactor `DFT` IO (#4530)

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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feat(AIA): integrate ChiselAIA again (#4509)

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=1`

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Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429)

This reverts commit 7fbc1cb42a2c96ef89a1dfd0f5f885ccada40c26.

feat(AIA): integrate ChiselAIA (#4378)

fix(PFEvent): use `CSRModule` for distribute_csr in PFEvent (#4321)

feat(dfx): integerate dfx components (#4312)

feat(busytable): support eliminate old vd in new dispatch (#4198)

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bo

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bound.
Level-2: Fetch Latency Bound, Fetch Bandwidth Bound, Branch
Missprediction, machine clears, Core Bound, Memory Bound.
Leval-3: L1 Bound, L2 Bound, L3 Bound, Mem Bound, Store Bound.

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feat(custom, csr): add two custom CSRs mcorepwr and mflushpwr to control power (#4164)

Co-authored-by: Zhu Yu <[email protected]>

area(trace, pcMem): Trace only get `startAddr` from pcmem

timing(redirectGen): fix timing of addr trans type exception

area(backend): only use startAddr in pcMem

area(backend): only pipe wakeupFromIQ and wakeupFromWB once

area(Backend): merge pcMem and pcTargetMem

feat(backend): NewDispatch

area(IssueQueue): encode exuOH as UInt to reduce storage (#4033)

fix(trace): remove traceTrap & tracePriv from trace pipeline

feat(trace): add trace buffer.

docs: add acknowledgements (#3861)

fix(dcsr): debug support critical error state

* support nmip, cetrig, extcause fileds in dcsr.
* critical error state enter dmode when dcsr.cetrig assert.

feat(difftest): add 'pc' and 'robidx' for store event (#3862)

feat(dbltrp) : add support for critical error (#3793)

fix(Backend): add vecLoadFinalIssueResp