1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput} 10import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 11import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 12import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 13import xiangshan.backend.datapath.WbConfig._ 14import xiangshan.backend.datapath._ 15import xiangshan.backend.dispatch.CoreDispatchTopDownIO 16import xiangshan.backend.exu.ExuBlock 17import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 18import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 19import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 20import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO} 21import xiangshan.frontend.{FtqPtr, FtqRead} 22import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 23 24class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 25 with HasXSParameter { 26 27 override def shouldBeInlined: Boolean = false 28 29 /* Only update the idx in mem-scheduler here 30 * Idx in other schedulers can be updated the same way if needed 31 * 32 * Also note that we filter out the 'stData issue-queues' when counting 33 */ 34 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 35 ibp.updateIdx(idx) 36 } 37 38 println(params.iqWakeUpParams) 39 40 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 41 schdCfg.bindBackendParam(params) 42 } 43 44 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 45 iqCfg.bindBackendParam(params) 46 } 47 48 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 49 exuCfg.bindBackendParam(params) 50 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 51 exuCfg.updateExuIdx(i) 52 } 53 54 println("[Backend] ExuConfigs:") 55 for (exuCfg <- params.allExuParams) { 56 val fuConfigs = exuCfg.fuConfigs 57 val wbPortConfigs = exuCfg.wbPortConfigs 58 val immType = exuCfg.immType 59 60 println("[Backend] " + 61 s"${exuCfg.name}: " + 62 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 63 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 64 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 65 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " 66 ) 67 require( 68 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 69 fuConfigs.map(_.writeIntRf).reduce(_ || _), 70 "int wb port has no priority" 71 ) 72 require( 73 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 74 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 75 "vec wb port has no priority" 76 ) 77 } 78 79 println(s"[Backend] all fu configs") 80 for (cfg <- FuConfig.allConfigs) { 81 println(s"[Backend] $cfg") 82 } 83 84 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 85 for ((port, seq) <- params.getRdPortParams(IntData())) { 86 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 87 } 88 89 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 90 for ((port, seq) <- params.getWbPortParams(IntData())) { 91 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 92 } 93 94 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 95 for ((port, seq) <- params.getRdPortParams(VecData())) { 96 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 97 } 98 99 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 100 for ((port, seq) <- params.getWbPortParams(VecData())) { 101 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 102 } 103 104 val ctrlBlock = LazyModule(new CtrlBlock(params)) 105 val pcTargetMem = LazyModule(new PcTargetMem(params)) 106 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 107 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 108 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 109 val cancelNetwork = LazyModule(new CancelNetwork(params)) 110 val dataPath = LazyModule(new DataPath(params)) 111 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 112 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 113 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 114 115 lazy val module = new BackendImp(this) 116} 117 118class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 119 with HasXSParameter { 120 implicit private val params = wrapper.params 121 122 val io = IO(new BackendIO()(p, wrapper.params)) 123 124 private val ctrlBlock = wrapper.ctrlBlock.module 125 private val pcTargetMem = wrapper.pcTargetMem.module 126 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 127 private val vfScheduler = wrapper.vfScheduler.get.module 128 private val memScheduler = wrapper.memScheduler.get.module 129 private val cancelNetwork = wrapper.cancelNetwork.module 130 private val dataPath = wrapper.dataPath.module 131 private val intExuBlock = wrapper.intExuBlock.get.module 132 private val vfExuBlock = wrapper.vfExuBlock.get.module 133 private val bypassNetwork = Module(new BypassNetwork) 134 private val wbDataPath = Module(new WbDataPath(params)) 135 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 136 137 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 138 intScheduler.io.toSchedulers.wakeupVec ++ 139 vfScheduler.io.toSchedulers.wakeupVec ++ 140 memScheduler.io.toSchedulers.wakeupVec 141 ).map(x => (x.bits.exuIdx, x)).toMap 142 143 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 144 145 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 146 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 147 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 148 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 149 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 150 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 151 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 152 153 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 154 155 private val vconfig = dataPath.io.vconfigReadPort.data 156 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 157 private val og0CancelOHFromDataPath: UInt = dataPath.io.og0CancelOH 158 private val og0CancelOHFromCancelNet: UInt = cancelNetwork.io.out.og0CancelOH 159 private val og0CancelOHFromFinalIssue: UInt = Wire(chiselTypeOf(dataPath.io.og0CancelOH)) 160 private val og0CancelOH: UInt = og0CancelOHFromDataPath | og0CancelOHFromCancelNet | og0CancelOHFromFinalIssue 161 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 162 163 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 164 ctrlBlock.io.frontend <> io.frontend 165 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 166 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 167 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 168 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 169 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 170 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 171 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 172 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 173 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 174 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 175 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 176 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 177 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 178 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 179 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 180 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 181 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 182 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 183 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 184 185 186 intScheduler.io.fromTop.hartId := io.fromTop.hartId 187 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 188 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 189 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 190 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 191 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 192 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 193 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 194 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 195 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 196 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 197 intScheduler.io.ldCancel := io.mem.ldCancel 198 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 199 200 memScheduler.io.fromTop.hartId := io.fromTop.hartId 201 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 202 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 203 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 204 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 205 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 206 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 207 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 208 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 209 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 210 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 211 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 212 sink.valid := source.valid 213 sink.bits := source.bits.robIdx 214 } 215 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 216 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 217 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 218 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 219 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 220 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 221 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 222 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 223 memScheduler.io.ldCancel := io.mem.ldCancel 224 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 225 226 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 227 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 228 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 229 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 230 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 231 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 232 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 233 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 234 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 235 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 236 vfScheduler.io.ldCancel := io.mem.ldCancel 237 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 238 239 cancelNetwork.io.in.int <> intScheduler.io.toDataPath 240 cancelNetwork.io.in.vf <> vfScheduler.io.toDataPath 241 cancelNetwork.io.in.mem <> memScheduler.io.toDataPath 242 cancelNetwork.io.in.og0CancelOH := og0CancelOHFromDataPath | og0CancelOHFromFinalIssue 243 cancelNetwork.io.in.og1CancelOH := og1CancelOH 244 intScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.int 245 vfScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.vf 246 memScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.mem 247 248 dataPath.io.hartId := io.fromTop.hartId 249 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 250 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 251 252 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 253 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 254 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 255 256 dataPath.io.ldCancel := io.mem.ldCancel 257 258 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 259 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 260 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 261 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 262 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 263 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 264 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 265 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 266 267 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 268 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 269 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 270 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 271 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 272 273 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeback).foreach { case (sink, source) => 274 sink.valid := source.valid 275 sink.bits.pdest := source.bits.uop.pdest 276 sink.bits.data := source.bits.data 277 } 278 279 280 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 281 for (i <- 0 until intExuBlock.io.in.length) { 282 for (j <- 0 until intExuBlock.io.in(i).length) { 283 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 284 NewPipelineConnect( 285 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 286 Mux( 287 bypassNetwork.io.toExus.int(i)(j).fire, 288 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 289 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 290 ) 291 ) 292 } 293 } 294 295 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 296 pcTargetMem.io.fromDataPathFtq := bypassNetwork.io.toExus.int.flatten.filter(_.bits.params.hasPredecode).map(_.bits.ftqIdx.get).toSeq 297 intExuBlock.io.in.flatten.filter(_.bits.params.hasPredecode).map(_.bits.predictInfo.get.target).zipWithIndex.foreach { 298 case (sink, i) => 299 sink := pcTargetMem.io.toExus(i) 300 } 301 302 private val csrio = intExuBlock.io.csrio.get 303 csrio.hartId := io.fromTop.hartId 304 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 305 csrio.fpu.isIllegal := false.B // Todo: remove it 306 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 307 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 308 309 val debugVconfig = dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 310 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 311 val debugVl = debugVconfig.vl 312 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 313 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 314 csrio.vpu.set_vstart.bits := 0.U 315 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 316 //Todo here need change design 317 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 318 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 319 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 320 csrio.exception := ctrlBlock.io.robio.exception 321 csrio.memExceptionVAddr := io.mem.exceptionVAddr 322 csrio.externalInterrupt := io.fromTop.externalInterrupt 323 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 324 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 325 csrio.perf <> io.perf 326 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 327 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 328 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 329 private val fenceio = intExuBlock.io.fenceio.get 330 io.fenceio <> fenceio 331 fenceio.disableSfence := csrio.disableSfence 332 333 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 334 for (i <- 0 until vfExuBlock.io.in.size) { 335 for (j <- 0 until vfExuBlock.io.in(i).size) { 336 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 337 NewPipelineConnect( 338 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 339 Mux( 340 bypassNetwork.io.toExus.vf(i)(j).fire, 341 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 342 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 343 ) 344 ) 345 346 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 347 } 348 } 349 350 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 351 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 352 353 wbDataPath.io.flush := ctrlBlock.io.redirect 354 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 355 wbDataPath.io.fromIntExu <> intExuBlock.io.out 356 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 357 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeback).foreach { case (sink, source) => 358 sink.valid := source.valid 359 source.ready := sink.ready 360 sink.bits.data := source.bits.data 361 sink.bits.pdest := source.bits.uop.pdest 362 sink.bits.robIdx := source.bits.uop.robIdx 363 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 364 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 365 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 366 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 367 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 368 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 369 sink.bits.debug := source.bits.debug 370 sink.bits.debugInfo := source.bits.uop.debugInfo 371 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 372 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 373 } 374 375 // to mem 376 private val memIssueParams = params.memSchdParams.get.issueBlockParams 377 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(_.fuConfigs.contains(FuConfig.LduCfg))) 378 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 379 380 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 381 for (i <- toMem.indices) { 382 for (j <- toMem(i).indices) { 383 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 384 val issueTimeout = 385 if (memExuBlocksHasLDU(i)(j)) 386 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 387 else 388 false.B 389 390 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty) { 391 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 392 memScheduler.io.loadFinalIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 393 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 394 memScheduler.io.loadFinalIssueResp(i)(j).bits.respType := RSFeedbackType.fuBusy 395 memScheduler.io.loadFinalIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 396 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 397 } 398 399 NewPipelineConnect( 400 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 401 Mux( 402 bypassNetwork.io.toExus.mem(i)(j).fire, 403 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 404 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 405 ) 406 ) 407 408 if (memScheduler.io.memAddrIssueResp(i).nonEmpty) { 409 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire 410 memScheduler.io.memAddrIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 411 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 412 memScheduler.io.memAddrIssueResp(i)(j).bits.respType := RSFeedbackType.fuIdle 413 memScheduler.io.memAddrIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 414 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 415 } 416 } 417 } 418 419 io.mem.redirect := ctrlBlock.io.redirect 420 private val memIssueUops = io.mem.issueLda ++ io.mem.issueHya ++ io.mem.issueSta ++ io.mem.issueStd ++ io.mem.issueVldu 421 memIssueUops.zip(toMem.flatten).foreach { case (sink, source) => 422 sink.valid := source.valid 423 source.ready := sink.ready 424 sink.bits.iqIdx := source.bits.iqIdx 425 sink.bits.isFirstIssue := source.bits.isFirstIssue 426 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 427 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 428 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 429 sink.bits.deqPortIdx := source.bits.deqPortIdx.getOrElse(0.U) 430 sink.bits.uop.fuType := source.bits.fuType 431 sink.bits.uop.fuOpType := source.bits.fuOpType 432 sink.bits.uop.imm := source.bits.imm 433 sink.bits.uop.robIdx := source.bits.robIdx 434 sink.bits.uop.pdest := source.bits.pdest 435 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 436 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 437 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 438 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 439 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 440 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 441 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 442 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 443 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 444 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 445 } 446 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 447 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 448 io.mem.tlbCsr := csrio.tlb 449 io.mem.csrCtrl := csrio.customCtrl 450 io.mem.sfence := fenceio.sfence 451 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 452 require(io.mem.loadPcRead.size == params.LduCnt) 453 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 454 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 455 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 456 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 457 require(toMem.head(i).bits.ftqIdx.isDefined && toMem.head(i).bits.ftqOffset.isDefined) 458 } 459 460 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 461 storePcRead := ctrlBlock.io.memStPcRead(i).data 462 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 463 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 464 require(toMem(1)(i).bits.ftqIdx.isDefined && toMem(1)(i).bits.ftqOffset.isDefined) 465 } 466 467 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 468 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 469 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHya(i).bits.uop.ftqPtr 470 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHya(i).bits.uop.ftqOffset 471 require(toMem(2)(i).bits.ftqIdx.isDefined && toMem(2)(i).bits.ftqOffset.isDefined) 472 }) 473 474 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 475 476 // mem io 477 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 478 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 479 480 private val intFinalIssueBlock = intExuBlock.io.in.flatten.toSeq.map(_ => false.B) 481 private val vfFinalIssueBlock = vfExuBlock.io.in.flatten.toSeq.map(_ => false.B) 482 private val memFinalIssueBlock = io.mem.issueUops.toSeq zip memExuBlocksHasLDU.flatten.toSeq map { 483 case (out, true) => RegNext(out.valid && !out.ready, false.B) 484 case (_, false) => false.B 485 } 486 println(s"[backend]: width of [int|vf|mem]FinalIssueBlock: ${intFinalIssueBlock.size}|${vfFinalIssueBlock.size}|${memFinalIssueBlock.size}") 487 og0CancelOHFromFinalIssue := VecInit(intFinalIssueBlock ++ vfFinalIssueBlock ++ memFinalIssueBlock).asUInt 488 489 io.frontendSfence := fenceio.sfence 490 io.frontendTlbCsr := csrio.tlb 491 io.frontendCsrCtrl := csrio.customCtrl 492 493 io.tlb <> csrio.tlb 494 495 io.csrCustomCtrl := csrio.customCtrl 496 497 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 498 499 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 500 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 501 502 io.debugRolling := ctrlBlock.io.debugRolling 503 504 dontTouch(memScheduler.io) 505 dontTouch(dataPath.io.toMemExu) 506 dontTouch(wbDataPath.io.fromMemExu) 507} 508 509class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 510 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 511 val flippedLda = true 512 // params alias 513 private val LoadQueueSize = VirtualLoadQueueSize 514 // In/Out // Todo: split it into one-direction bundle 515 val lsqEnqIO = Flipped(new LsqEnqIO) 516 val robLsqIO = new RobLsqIO 517 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 518 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 519 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 520 val ldCancel = Vec(params.LduCnt + params.HyuCnt, Flipped(new LoadCancelIO)) 521 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 522 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 523 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 524 // Input 525 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 526 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 527 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 528 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 529 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 530 val writebackVlda = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 531 532 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 533 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 534 val memoryViolation = Flipped(ValidIO(new Redirect)) 535 val exceptionVAddr = Input(UInt(VAddrBits.W)) 536 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 537 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 538 539 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 540 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 541 542 val lqCanAccept = Input(Bool()) 543 val sqCanAccept = Input(Bool()) 544 545 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 546 val stIssuePtr = Input(new SqPtr()) 547 548 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 549 550 val debugLS = Flipped(Output(new DebugLSIO)) 551 552 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 553 // Output 554 val redirect = ValidIO(new Redirect) // rob flush MemBlock 555 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 556 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 557 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 558 val issueHya = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 559 // hybrid unit store data use this 560 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(isVector = true)))) 561 562 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 563 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 564 565 val tlbCsr = Output(new TlbCsrBundle) 566 val csrCtrl = Output(new CustomCSRCtrlIO) 567 val sfence = Output(new SfenceBundle) 568 val isStoreException = Output(Bool()) 569 570 def issueUops = issueLda ++ issueSta ++ issueStd ++ issueHya ++ issueVldu 571 572 def writeback = writebackLda ++ writebackSta ++ writebackHyuLda ++ writebackHyuSta ++ writebackStd ++ writebackVlda 573 574 // make this function private to avoid flip twice, both in Backend and XSCore 575 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 576 val issLdas = if (flippedLda) Seq(issueLdas(1), issueLdas(0)) else issueLdas 577 (issLdas ++ issueStas ++ issueStds ++ issueVldus).toSeq 578 } 579 580 // make this function private to avoid flip twice, both in Backend and XSCore 581 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 582 val wbLdas = if (flippedLda) Seq(writebackLdas(1), writebackLdas(0)) else writebackLdas 583 (wbLdas ++ writebackStas ++ writebackStds ++ writebackVldus).toSeq 584 } 585 586 def issueUopsToMem: Seq[DecoupledIO[MemExuInput]] = { 587 (issueLdas ++ issueStas ++ issueStds ++ issueVldus).toSeq 588 } 589 590 def writeBackToBackend: Seq[DecoupledIO[MemExuOutput]] = { 591 (writebackLdas ++ writebackStas ++ writebackStds ++ writebackVldus).toSeq 592 } 593} 594 595class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 596 val fromTop = new Bundle { 597 val hartId = Input(UInt(8.W)) 598 val externalInterrupt = new ExternalInterruptIO 599 } 600 601 val toTop = new Bundle { 602 val cpuHalted = Output(Bool()) 603 } 604 605 val fenceio = new FenceIO 606 // Todo: merge these bundles into BackendFrontendIO 607 val frontend = Flipped(new FrontendToCtrlIO) 608 val frontendSfence = Output(new SfenceBundle) 609 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 610 val frontendTlbCsr = Output(new TlbCsrBundle) 611 // distributed csr write 612 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 613 614 val mem = new BackendMemIO 615 616 val perf = Input(new PerfCounterIO) 617 618 val tlb = Output(new TlbCsrBundle) 619 620 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 621 622 val debugTopDown = new Bundle { 623 val fromRob = new RobCoreTopDownIO 624 val fromCore = new CoreDispatchTopDownIO 625 } 626 val debugRolling = new RobDebugRollingIO 627} 628