1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 10import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 11import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 12import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 13import xiangshan.backend.datapath.WbConfig._ 14import xiangshan.backend.datapath._ 15import xiangshan.backend.dispatch.CoreDispatchTopDownIO 16import xiangshan.backend.exu.ExuBlock 17import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 18import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 19import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 20import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO} 21import xiangshan.frontend.{FtqPtr, FtqRead} 22import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 23 24class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 25 with HasXSParameter { 26 27 override def shouldBeInlined: Boolean = false 28 29 /* Only update the idx in mem-scheduler here 30 * Idx in other schedulers can be updated the same way if needed 31 * 32 * Also note that we filter out the 'stData issue-queues' when counting 33 */ 34 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0 && iq.VstdCnt == 0).zipWithIndex) { 35 ibp.updateIdx(idx) 36 } 37 38 println(params.iqWakeUpParams) 39 40 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 41 schdCfg.bindBackendParam(params) 42 } 43 44 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 45 iqCfg.bindBackendParam(params) 46 } 47 48 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 49 exuCfg.bindBackendParam(params) 50 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 51 exuCfg.updateExuIdx(i) 52 } 53 54 println("[Backend] ExuConfigs:") 55 for (exuCfg <- params.allExuParams) { 56 val fuConfigs = exuCfg.fuConfigs 57 val wbPortConfigs = exuCfg.wbPortConfigs 58 val immType = exuCfg.immType 59 60 println("[Backend] " + 61 s"${exuCfg.name}: " + 62 (if (exuCfg.fakeUnit) "fake, " else "") + 63 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 64 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 65 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 66 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 67 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 68 s"srcReg(${exuCfg.numRegSrc})" 69 ) 70 require( 71 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 72 fuConfigs.map(_.writeIntRf).reduce(_ || _), 73 "int wb port has no priority" 74 ) 75 require( 76 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 77 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 78 "vec wb port has no priority" 79 ) 80 } 81 82 println(s"[Backend] all fu configs") 83 for (cfg <- FuConfig.allConfigs) { 84 println(s"[Backend] $cfg") 85 } 86 87 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 88 for ((port, seq) <- params.getRdPortParams(IntData())) { 89 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 90 } 91 92 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 93 for ((port, seq) <- params.getWbPortParams(IntData())) { 94 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 95 } 96 97 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 98 for ((port, seq) <- params.getRdPortParams(VecData())) { 99 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 100 } 101 102 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 103 for ((port, seq) <- params.getWbPortParams(VecData())) { 104 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 105 } 106 107 val ctrlBlock = LazyModule(new CtrlBlock(params)) 108 val pcTargetMem = LazyModule(new PcTargetMem(params)) 109 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 110 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 111 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 112 val cancelNetwork = LazyModule(new CancelNetwork(params)) 113 val dataPath = LazyModule(new DataPath(params)) 114 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 115 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 116 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 117 118 lazy val module = new BackendImp(this) 119} 120 121class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 122 with HasXSParameter { 123 implicit private val params = wrapper.params 124 125 val io = IO(new BackendIO()(p, wrapper.params)) 126 127 private val ctrlBlock = wrapper.ctrlBlock.module 128 private val pcTargetMem = wrapper.pcTargetMem.module 129 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 130 private val vfScheduler = wrapper.vfScheduler.get.module 131 private val memScheduler = wrapper.memScheduler.get.module 132 private val cancelNetwork = wrapper.cancelNetwork.module 133 private val dataPath = wrapper.dataPath.module 134 private val intExuBlock = wrapper.intExuBlock.get.module 135 private val vfExuBlock = wrapper.vfExuBlock.get.module 136 private val bypassNetwork = Module(new BypassNetwork) 137 private val wbDataPath = Module(new WbDataPath(params)) 138 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 139 140 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 141 intScheduler.io.toSchedulers.wakeupVec ++ 142 vfScheduler.io.toSchedulers.wakeupVec ++ 143 memScheduler.io.toSchedulers.wakeupVec 144 ).map(x => (x.bits.exuIdx, x)).toMap 145 146 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 147 148 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 149 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 150 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 151 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 152 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 153 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 154 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 155 156 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 157 158 private val vconfig = dataPath.io.vconfigReadPort.data 159 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 160 private val og0CancelOHFromDataPath: UInt = dataPath.io.og0CancelOH 161 private val og0CancelOHFromCancelNet: UInt = cancelNetwork.io.out.og0CancelOH 162 private val og0CancelOHFromFinalIssue: UInt = Wire(chiselTypeOf(dataPath.io.og0CancelOH)) 163 private val og0CancelOH: UInt = og0CancelOHFromDataPath | og0CancelOHFromCancelNet | og0CancelOHFromFinalIssue 164 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 165 166 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 167 ctrlBlock.io.frontend <> io.frontend 168 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 169 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 170 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 171 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 172 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 173 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 174 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 175 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 176 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 177 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 178 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 179 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 180 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 181 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 182 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 183 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 184 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 185 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 186 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 187 188 189 intScheduler.io.fromTop.hartId := io.fromTop.hartId 190 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 191 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 192 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 193 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 194 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 195 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 196 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 197 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 198 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 199 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 200 intScheduler.io.ldCancel := io.mem.ldCancel 201 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 202 203 memScheduler.io.fromTop.hartId := io.fromTop.hartId 204 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 205 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 206 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 207 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 208 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 209 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 210 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 211 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 212 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 213 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 214 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 215 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 216 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 217 sink.valid := source.valid 218 sink.bits := source.bits.robIdx 219 } 220 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 221 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 222 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 223 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 224 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 225 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 226 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 227 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 228 memScheduler.io.ldCancel := io.mem.ldCancel 229 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 230 231 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 232 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 233 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 234 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 235 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 236 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 237 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 238 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 239 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 240 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 241 vfScheduler.io.ldCancel := io.mem.ldCancel 242 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 243 244 cancelNetwork.io.in.int <> intScheduler.io.toDataPath 245 cancelNetwork.io.in.vf <> vfScheduler.io.toDataPath 246 cancelNetwork.io.in.mem <> memScheduler.io.toDataPath 247 cancelNetwork.io.in.og0CancelOH := og0CancelOHFromDataPath | og0CancelOHFromFinalIssue 248 cancelNetwork.io.in.og1CancelOH := og1CancelOH 249 intScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.int 250 vfScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.vf 251 memScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.mem 252 253 dataPath.io.hartId := io.fromTop.hartId 254 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 255 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 256 dataPath.io.vldReadPort.addr := wbDataPath.io.oldVdAddrToDataPath 257 258 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 259 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 260 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 261 262 dataPath.io.ldCancel := io.mem.ldCancel 263 264 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 265 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 266 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 267 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 268 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 269 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 270 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 271 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 272 273 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 274 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 275 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 276 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 277 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 278 279 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 280 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 281 s"io.mem.writeback(${io.mem.writeBack.size})" 282 ) 283 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 284 sink.valid := source.valid 285 sink.bits.pdest := source.bits.uop.pdest 286 sink.bits.data := source.bits.data 287 } 288 289 290 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 291 for (i <- 0 until intExuBlock.io.in.length) { 292 for (j <- 0 until intExuBlock.io.in(i).length) { 293 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 294 NewPipelineConnect( 295 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 296 Mux( 297 bypassNetwork.io.toExus.int(i)(j).fire, 298 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 299 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 300 ) 301 ) 302 } 303 } 304 305 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 306 pcTargetMem.io.fromDataPathFtq := bypassNetwork.io.toExus.int.flatten.filter(_.bits.params.hasPredecode).map(_.bits.ftqIdx.get).toSeq 307 intExuBlock.io.in.flatten.filter(_.bits.params.hasPredecode).map(_.bits.predictInfo.get.target).zipWithIndex.foreach { 308 case (sink, i) => 309 sink := pcTargetMem.io.toExus(i) 310 } 311 312 private val csrio = intExuBlock.io.csrio.get 313 csrio.hartId := io.fromTop.hartId 314 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 315 csrio.fpu.isIllegal := false.B // Todo: remove it 316 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 317 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 318 319 val debugVconfig = dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 320 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 321 val debugVl = debugVconfig.vl 322 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 323 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 324 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 325 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 326 //Todo here need change design 327 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 328 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 329 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 330 csrio.exception := ctrlBlock.io.robio.exception 331 csrio.memExceptionVAddr := io.mem.exceptionVAddr 332 csrio.externalInterrupt := io.fromTop.externalInterrupt 333 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 334 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 335 csrio.perf <> io.perf 336 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 337 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 338 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 339 private val fenceio = intExuBlock.io.fenceio.get 340 io.fenceio <> fenceio 341 fenceio.disableSfence := csrio.disableSfence 342 343 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 344 for (i <- 0 until vfExuBlock.io.in.size) { 345 for (j <- 0 until vfExuBlock.io.in(i).size) { 346 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 347 NewPipelineConnect( 348 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 349 Mux( 350 bypassNetwork.io.toExus.vf(i)(j).fire, 351 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 352 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 353 ) 354 ) 355 356 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 357 } 358 } 359 360 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 361 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 362 363 wbDataPath.io.flush := ctrlBlock.io.redirect 364 wbDataPath.io.oldVdDataFromDataPath := dataPath.io.vldReadPort.data 365 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 366 wbDataPath.io.fromIntExu <> intExuBlock.io.out 367 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 368 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 369 sink.valid := source.valid 370 source.ready := sink.ready 371 sink.bits.data := source.bits.data 372 sink.bits.pdest := source.bits.uop.pdest 373 sink.bits.robIdx := source.bits.uop.robIdx 374 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 375 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 376 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 377 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 378 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 379 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 380 sink.bits.debug := source.bits.debug 381 sink.bits.debugInfo := source.bits.uop.debugInfo 382 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 383 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 384 sink.bits.vls.foreach(x => { 385 x.vdIdx := source.bits.vdIdx.get 386 x.vpu := source.bits.uop.vpu 387 x.oldVdPsrc := source.bits.uop.psrc(2) 388 }) 389 } 390 391 // to mem 392 private val memIssueParams = params.memSchdParams.get.issueBlockParams 393 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 394 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 395 396 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 397 for (i <- toMem.indices) { 398 for (j <- toMem(i).indices) { 399 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 400 val issueTimeout = 401 if (memExuBlocksHasLDU(i)(j)) 402 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 403 else 404 false.B 405 406 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 407 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 408 memScheduler.io.loadFinalIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 409 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 410 memScheduler.io.loadFinalIssueResp(i)(j).bits.respType := RSFeedbackType.fuBusy 411 memScheduler.io.loadFinalIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 412 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 413 } 414 415 NewPipelineConnect( 416 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 417 Mux( 418 bypassNetwork.io.toExus.mem(i)(j).fire, 419 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 420 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 421 ) 422 ) 423 424 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 425 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 426 memScheduler.io.memAddrIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 427 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 428 memScheduler.io.memAddrIssueResp(i)(j).bits.respType := RSFeedbackType.fuIdle 429 memScheduler.io.memAddrIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 430 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 431 } 432 } 433 } 434 435 io.mem.redirect := ctrlBlock.io.redirect 436 private val memIssueUops = 437 Seq(io.mem.issueLda(0)) ++ Seq(io.mem.issueSta(0)) ++ 438 io.mem.issueHylda ++ io.mem.issueHysta ++ 439 Seq(io.mem.issueLda(1)) ++ 440 io.mem.issueVldu ++ 441 io.mem.issueStd 442 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 443 sink.valid := source.valid 444 source.ready := sink.ready 445 sink.bits.iqIdx := source.bits.iqIdx 446 sink.bits.isFirstIssue := source.bits.isFirstIssue 447 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 448 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 449 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 450 sink.bits.deqPortIdx := source.bits.deqLdExuIdx.getOrElse(0.U) 451 sink.bits.uop.fuType := source.bits.fuType 452 sink.bits.uop.fuOpType := source.bits.fuOpType 453 sink.bits.uop.imm := source.bits.imm 454 sink.bits.uop.robIdx := source.bits.robIdx 455 sink.bits.uop.pdest := source.bits.pdest 456 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 457 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 458 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 459 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 460 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 461 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 462 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 463 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 464 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 465 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 466 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 467 } 468 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 469 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 470 io.mem.tlbCsr := csrio.tlb 471 io.mem.csrCtrl := csrio.customCtrl 472 io.mem.sfence := fenceio.sfence 473 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 474 require(io.mem.loadPcRead.size == params.LduCnt) 475 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 476 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 477 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 478 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 479 require(toMem.head(i).bits.ftqIdx.isDefined && toMem.head(i).bits.ftqOffset.isDefined) 480 } 481 482 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 483 storePcRead := ctrlBlock.io.memStPcRead(i).data 484 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 485 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 486 require(toMem(1)(i).bits.ftqIdx.isDefined && toMem(1)(i).bits.ftqOffset.isDefined) 487 } 488 489 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 490 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 491 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 492 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 493 require(toMem(2)(i).bits.ftqIdx.isDefined && toMem(2)(i).bits.ftqOffset.isDefined) 494 }) 495 496 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 497 498 // mem io 499 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 500 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 501 502 private val intFinalIssueBlock = intExuBlock.io.in.flatten.toSeq.map(_ => false.B) 503 private val vfFinalIssueBlock = vfExuBlock.io.in.flatten.toSeq.map(_ => false.B) 504 private val memFinalIssueBlock = io.mem.issueUops.toSeq zip memExuBlocksHasLDU.flatten.toSeq map { 505 case (out, true) => RegNext(out.valid && !out.ready, false.B) 506 case (_, false) => false.B 507 } 508 println(s"[backend]: width of [int|vf|mem]FinalIssueBlock: ${intFinalIssueBlock.size}|${vfFinalIssueBlock.size}|${memFinalIssueBlock.size}") 509 og0CancelOHFromFinalIssue := VecInit(intFinalIssueBlock ++ vfFinalIssueBlock ++ memFinalIssueBlock).asUInt 510 511 io.frontendSfence := fenceio.sfence 512 io.frontendTlbCsr := csrio.tlb 513 io.frontendCsrCtrl := csrio.customCtrl 514 515 io.tlb <> csrio.tlb 516 517 io.csrCustomCtrl := csrio.customCtrl 518 519 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 520 521 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 522 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 523 524 io.debugRolling := ctrlBlock.io.debugRolling 525 526 dontTouch(memScheduler.io) 527 dontTouch(dataPath.io.toMemExu) 528 dontTouch(wbDataPath.io.fromMemExu) 529} 530 531class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 532 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 533 val flippedLda = true 534 // params alias 535 private val LoadQueueSize = VirtualLoadQueueSize 536 // In/Out // Todo: split it into one-direction bundle 537 val lsqEnqIO = Flipped(new LsqEnqIO) 538 val robLsqIO = new RobLsqIO 539 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 540 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 541 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 542 val ldCancel = Vec(params.LduCnt + params.HyuCnt, Flipped(new LoadCancelIO)) 543 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 544 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 545 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 546 // Input 547 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 548 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 549 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 550 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 551 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 552 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 553 554 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 555 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 556 val memoryViolation = Flipped(ValidIO(new Redirect)) 557 val exceptionVAddr = Input(UInt(VAddrBits.W)) 558 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 559 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 560 val sqDeqPtr = Input(new SqPtr) 561 val lqDeqPtr = Input(new LqPtr) 562 563 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 564 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 565 566 val lqCanAccept = Input(Bool()) 567 val sqCanAccept = Input(Bool()) 568 569 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 570 val stIssuePtr = Input(new SqPtr()) 571 572 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 573 574 val debugLS = Flipped(Output(new DebugLSIO)) 575 576 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 577 // Output 578 val redirect = ValidIO(new Redirect) // rob flush MemBlock 579 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 580 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 581 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 582 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 583 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 584 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 585 586 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 587 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 588 589 val tlbCsr = Output(new TlbCsrBundle) 590 val csrCtrl = Output(new CustomCSRCtrlIO) 591 val sfence = Output(new SfenceBundle) 592 val isStoreException = Output(Bool()) 593 594 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 595 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 596 Seq(issueLda(0)) ++ Seq(issueSta(0)) ++ 597 issueHylda ++ issueHysta ++ 598 Seq(issueLda(1)) ++ 599 issueVldu ++ 600 issueStd 601 } 602 603 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 604 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 605 Seq(writebackLda(0)) ++ Seq(writebackSta(0)) ++ 606 writebackHyuLda ++ writebackHyuSta ++ 607 Seq(writebackLda(1)) ++ 608 writebackVldu ++ 609 writebackStd 610 } 611} 612 613class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 614 val fromTop = new Bundle { 615 val hartId = Input(UInt(8.W)) 616 val externalInterrupt = new ExternalInterruptIO 617 } 618 619 val toTop = new Bundle { 620 val cpuHalted = Output(Bool()) 621 } 622 623 val fenceio = new FenceIO 624 // Todo: merge these bundles into BackendFrontendIO 625 val frontend = Flipped(new FrontendToCtrlIO) 626 val frontendSfence = Output(new SfenceBundle) 627 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 628 val frontendTlbCsr = Output(new TlbCsrBundle) 629 // distributed csr write 630 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 631 632 val mem = new BackendMemIO 633 634 val perf = Input(new PerfCounterIO) 635 636 val tlb = Output(new TlbCsrBundle) 637 638 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 639 640 val debugTopDown = new Bundle { 641 val fromRob = new RobCoreTopDownIO 642 val fromCore = new CoreDispatchTopDownIO 643 } 644 val debugRolling = new RobDebugRollingIO 645} 646