1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput} 10import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 11import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 12import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 13import xiangshan.backend.datapath.WbConfig._ 14import xiangshan.backend.datapath._ 15import xiangshan.backend.dispatch.CoreDispatchTopDownIO 16import xiangshan.backend.exu.ExuBlock 17import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 18import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 19import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 20import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO} 21import xiangshan.frontend.{FtqPtr, FtqRead} 22import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 23 24class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 25 with HasXSParameter { 26 27 override def shouldBeInlined: Boolean = false 28 29 /* Only update the idx in mem-scheduler here 30 * Idx in other schedulers can be updated the same way if needed 31 * 32 * Also note that we filter out the 'stData issue-queues' when counting 33 */ 34 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 35 ibp.updateIdx(idx) 36 } 37 38 println(params.iqWakeUpParams) 39 40 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 41 schdCfg.bindBackendParam(params) 42 } 43 44 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 45 iqCfg.bindBackendParam(params) 46 } 47 48 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 49 exuCfg.bindBackendParam(params) 50 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 51 exuCfg.updateExuIdx(i) 52 } 53 54 println("[Backend] ExuConfigs:") 55 for (exuCfg <- params.allExuParams) { 56 val fuConfigs = exuCfg.fuConfigs 57 val wbPortConfigs = exuCfg.wbPortConfigs 58 val immType = exuCfg.immType 59 60 println("[Backend] " + 61 s"${exuCfg.name}: " + 62 (if (exuCfg.fakeUnit) "fake, " else "") + 63 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 64 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 65 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 66 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 67 s"srcReg(${exuCfg.numRegSrc})" 68 ) 69 require( 70 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 71 fuConfigs.map(_.writeIntRf).reduce(_ || _), 72 "int wb port has no priority" 73 ) 74 require( 75 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 76 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 77 "vec wb port has no priority" 78 ) 79 } 80 81 println(s"[Backend] all fu configs") 82 for (cfg <- FuConfig.allConfigs) { 83 println(s"[Backend] $cfg") 84 } 85 86 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 87 for ((port, seq) <- params.getRdPortParams(IntData())) { 88 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 89 } 90 91 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 92 for ((port, seq) <- params.getWbPortParams(IntData())) { 93 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 94 } 95 96 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 97 for ((port, seq) <- params.getRdPortParams(VecData())) { 98 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 99 } 100 101 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 102 for ((port, seq) <- params.getWbPortParams(VecData())) { 103 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 104 } 105 106 val ctrlBlock = LazyModule(new CtrlBlock(params)) 107 val pcTargetMem = LazyModule(new PcTargetMem(params)) 108 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 109 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 110 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 111 val cancelNetwork = LazyModule(new CancelNetwork(params)) 112 val dataPath = LazyModule(new DataPath(params)) 113 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 114 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 115 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 116 117 lazy val module = new BackendImp(this) 118} 119 120class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 121 with HasXSParameter { 122 implicit private val params = wrapper.params 123 124 val io = IO(new BackendIO()(p, wrapper.params)) 125 126 private val ctrlBlock = wrapper.ctrlBlock.module 127 private val pcTargetMem = wrapper.pcTargetMem.module 128 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 129 private val vfScheduler = wrapper.vfScheduler.get.module 130 private val memScheduler = wrapper.memScheduler.get.module 131 private val cancelNetwork = wrapper.cancelNetwork.module 132 private val dataPath = wrapper.dataPath.module 133 private val intExuBlock = wrapper.intExuBlock.get.module 134 private val vfExuBlock = wrapper.vfExuBlock.get.module 135 private val bypassNetwork = Module(new BypassNetwork) 136 private val wbDataPath = Module(new WbDataPath(params)) 137 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 138 139 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 140 intScheduler.io.toSchedulers.wakeupVec ++ 141 vfScheduler.io.toSchedulers.wakeupVec ++ 142 memScheduler.io.toSchedulers.wakeupVec 143 ).map(x => (x.bits.exuIdx, x)).toMap 144 145 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 146 147 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 148 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 149 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 150 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 151 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 152 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 153 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 154 155 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 156 157 private val vconfig = dataPath.io.vconfigReadPort.data 158 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 159 private val og0CancelOHFromDataPath: UInt = dataPath.io.og0CancelOH 160 private val og0CancelOHFromCancelNet: UInt = cancelNetwork.io.out.og0CancelOH 161 private val og0CancelOHFromFinalIssue: UInt = Wire(chiselTypeOf(dataPath.io.og0CancelOH)) 162 private val og0CancelOH: UInt = og0CancelOHFromDataPath | og0CancelOHFromCancelNet | og0CancelOHFromFinalIssue 163 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 164 165 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 166 ctrlBlock.io.frontend <> io.frontend 167 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 168 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 169 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 170 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 171 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 172 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 173 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 174 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 175 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 176 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 177 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 178 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 179 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 180 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 181 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 182 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 183 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 184 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 185 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 186 187 188 intScheduler.io.fromTop.hartId := io.fromTop.hartId 189 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 190 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 191 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 192 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 193 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 194 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 195 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 196 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 197 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 198 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 199 intScheduler.io.ldCancel := io.mem.ldCancel 200 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 201 202 memScheduler.io.fromTop.hartId := io.fromTop.hartId 203 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 204 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 205 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 206 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 207 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 208 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 209 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 210 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 211 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 212 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 213 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 214 sink.valid := source.valid 215 sink.bits := source.bits.robIdx 216 } 217 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 218 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 219 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 220 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 221 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 222 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 223 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 224 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 225 memScheduler.io.ldCancel := io.mem.ldCancel 226 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 227 228 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 229 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 230 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 231 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 232 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 233 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 234 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 235 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 236 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 237 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 238 vfScheduler.io.ldCancel := io.mem.ldCancel 239 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 240 241 cancelNetwork.io.in.int <> intScheduler.io.toDataPath 242 cancelNetwork.io.in.vf <> vfScheduler.io.toDataPath 243 cancelNetwork.io.in.mem <> memScheduler.io.toDataPath 244 cancelNetwork.io.in.og0CancelOH := og0CancelOHFromDataPath | og0CancelOHFromFinalIssue 245 cancelNetwork.io.in.og1CancelOH := og1CancelOH 246 intScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.int 247 vfScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.vf 248 memScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.mem 249 250 dataPath.io.hartId := io.fromTop.hartId 251 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 252 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 253 254 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 255 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 256 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 257 258 dataPath.io.ldCancel := io.mem.ldCancel 259 260 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 261 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 262 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 263 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 264 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 265 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 266 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 267 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 268 269 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 270 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 271 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 272 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 273 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 274 275 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 276 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 277 s"io.mem.writeback(${io.mem.writeBack.size})" 278 ) 279 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 280 sink.valid := source.valid 281 sink.bits.pdest := source.bits.uop.pdest 282 sink.bits.data := source.bits.data 283 } 284 285 286 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 287 for (i <- 0 until intExuBlock.io.in.length) { 288 for (j <- 0 until intExuBlock.io.in(i).length) { 289 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 290 NewPipelineConnect( 291 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 292 Mux( 293 bypassNetwork.io.toExus.int(i)(j).fire, 294 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 295 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 296 ) 297 ) 298 } 299 } 300 301 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 302 pcTargetMem.io.fromDataPathFtq := bypassNetwork.io.toExus.int.flatten.filter(_.bits.params.hasPredecode).map(_.bits.ftqIdx.get).toSeq 303 intExuBlock.io.in.flatten.filter(_.bits.params.hasPredecode).map(_.bits.predictInfo.get.target).zipWithIndex.foreach { 304 case (sink, i) => 305 sink := pcTargetMem.io.toExus(i) 306 } 307 308 private val csrio = intExuBlock.io.csrio.get 309 csrio.hartId := io.fromTop.hartId 310 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 311 csrio.fpu.isIllegal := false.B // Todo: remove it 312 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 313 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 314 315 val debugVconfig = dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 316 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 317 val debugVl = debugVconfig.vl 318 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 319 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 320 csrio.vpu.set_vstart.bits := 0.U 321 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 322 //Todo here need change design 323 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 324 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 325 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 326 csrio.exception := ctrlBlock.io.robio.exception 327 csrio.memExceptionVAddr := io.mem.exceptionVAddr 328 csrio.externalInterrupt := io.fromTop.externalInterrupt 329 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 330 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 331 csrio.perf <> io.perf 332 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 333 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 334 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 335 private val fenceio = intExuBlock.io.fenceio.get 336 io.fenceio <> fenceio 337 fenceio.disableSfence := csrio.disableSfence 338 339 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 340 for (i <- 0 until vfExuBlock.io.in.size) { 341 for (j <- 0 until vfExuBlock.io.in(i).size) { 342 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 343 NewPipelineConnect( 344 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 345 Mux( 346 bypassNetwork.io.toExus.vf(i)(j).fire, 347 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 348 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 349 ) 350 ) 351 352 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 353 } 354 } 355 356 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 357 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 358 359 wbDataPath.io.flush := ctrlBlock.io.redirect 360 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 361 wbDataPath.io.fromIntExu <> intExuBlock.io.out 362 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 363 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 364 sink.valid := source.valid 365 source.ready := sink.ready 366 sink.bits.data := source.bits.data 367 sink.bits.pdest := source.bits.uop.pdest 368 sink.bits.robIdx := source.bits.uop.robIdx 369 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 370 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 371 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 372 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 373 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 374 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 375 sink.bits.debug := source.bits.debug 376 sink.bits.debugInfo := source.bits.uop.debugInfo 377 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 378 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 379 } 380 381 // to mem 382 private val memIssueParams = params.memSchdParams.get.issueBlockParams 383 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 384 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 385 386 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 387 for (i <- toMem.indices) { 388 for (j <- toMem(i).indices) { 389 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 390 val issueTimeout = 391 if (memExuBlocksHasLDU(i)(j)) 392 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 393 else 394 false.B 395 396 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 397 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 398 memScheduler.io.loadFinalIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 399 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 400 memScheduler.io.loadFinalIssueResp(i)(j).bits.respType := RSFeedbackType.fuBusy 401 memScheduler.io.loadFinalIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 402 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 403 } 404 405 NewPipelineConnect( 406 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 407 Mux( 408 bypassNetwork.io.toExus.mem(i)(j).fire, 409 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 410 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 411 ) 412 ) 413 414 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 415 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire 416 memScheduler.io.memAddrIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 417 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 418 memScheduler.io.memAddrIssueResp(i)(j).bits.respType := RSFeedbackType.fuIdle 419 memScheduler.io.memAddrIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 420 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 421 } 422 } 423 } 424 425 io.mem.redirect := ctrlBlock.io.redirect 426 private val memIssueUops = 427 Seq(io.mem.issueLda(0)) ++ Seq(io.mem.issueSta(0)) ++ 428 io.mem.issueHylda ++ io.mem.issueHysta ++ 429 Seq(io.mem.issueLda(1)) ++ 430 io.mem.issueVldu ++ 431 io.mem.issueStd 432 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 433 sink.valid := source.valid 434 source.ready := sink.ready 435 sink.bits.iqIdx := source.bits.iqIdx 436 sink.bits.isFirstIssue := source.bits.isFirstIssue 437 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 438 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 439 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 440 sink.bits.deqPortIdx := source.bits.deqPortIdx.getOrElse(0.U) 441 sink.bits.uop.fuType := source.bits.fuType 442 sink.bits.uop.fuOpType := source.bits.fuOpType 443 sink.bits.uop.imm := source.bits.imm 444 sink.bits.uop.robIdx := source.bits.robIdx 445 sink.bits.uop.pdest := source.bits.pdest 446 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 447 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 448 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 449 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 450 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 451 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 452 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 453 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 454 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 455 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 456 } 457 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 458 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 459 io.mem.tlbCsr := csrio.tlb 460 io.mem.csrCtrl := csrio.customCtrl 461 io.mem.sfence := fenceio.sfence 462 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 463 require(io.mem.loadPcRead.size == params.LduCnt) 464 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 465 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 466 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 467 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 468 require(toMem.head(i).bits.ftqIdx.isDefined && toMem.head(i).bits.ftqOffset.isDefined) 469 } 470 471 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 472 storePcRead := ctrlBlock.io.memStPcRead(i).data 473 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 474 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 475 require(toMem(1)(i).bits.ftqIdx.isDefined && toMem(1)(i).bits.ftqOffset.isDefined) 476 } 477 478 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 479 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 480 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 481 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 482 require(toMem(2)(i).bits.ftqIdx.isDefined && toMem(2)(i).bits.ftqOffset.isDefined) 483 }) 484 485 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 486 487 // mem io 488 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 489 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 490 491 private val intFinalIssueBlock = intExuBlock.io.in.flatten.toSeq.map(_ => false.B) 492 private val vfFinalIssueBlock = vfExuBlock.io.in.flatten.toSeq.map(_ => false.B) 493 private val memFinalIssueBlock = io.mem.issueUops.toSeq zip memExuBlocksHasLDU.flatten.toSeq map { 494 case (out, true) => RegNext(out.valid && !out.ready, false.B) 495 case (_, false) => false.B 496 } 497 println(s"[backend]: width of [int|vf|mem]FinalIssueBlock: ${intFinalIssueBlock.size}|${vfFinalIssueBlock.size}|${memFinalIssueBlock.size}") 498 og0CancelOHFromFinalIssue := VecInit(intFinalIssueBlock ++ vfFinalIssueBlock ++ memFinalIssueBlock).asUInt 499 500 io.frontendSfence := fenceio.sfence 501 io.frontendTlbCsr := csrio.tlb 502 io.frontendCsrCtrl := csrio.customCtrl 503 504 io.tlb <> csrio.tlb 505 506 io.csrCustomCtrl := csrio.customCtrl 507 508 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 509 510 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 511 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 512 513 io.debugRolling := ctrlBlock.io.debugRolling 514 515 dontTouch(memScheduler.io) 516 dontTouch(dataPath.io.toMemExu) 517 dontTouch(wbDataPath.io.fromMemExu) 518} 519 520class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 521 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 522 val flippedLda = true 523 // params alias 524 private val LoadQueueSize = VirtualLoadQueueSize 525 // In/Out // Todo: split it into one-direction bundle 526 val lsqEnqIO = Flipped(new LsqEnqIO) 527 val robLsqIO = new RobLsqIO 528 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 529 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 530 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 531 val ldCancel = Vec(params.LduCnt + params.HyuCnt, Flipped(new LoadCancelIO)) 532 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 533 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 534 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 535 // Input 536 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 537 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 538 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 539 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 540 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 541 val writebackVlda = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 542 543 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 544 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 545 val memoryViolation = Flipped(ValidIO(new Redirect)) 546 val exceptionVAddr = Input(UInt(VAddrBits.W)) 547 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 548 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 549 550 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 551 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 552 553 val lqCanAccept = Input(Bool()) 554 val sqCanAccept = Input(Bool()) 555 556 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 557 val stIssuePtr = Input(new SqPtr()) 558 559 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 560 561 val debugLS = Flipped(Output(new DebugLSIO)) 562 563 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 564 // Output 565 val redirect = ValidIO(new Redirect) // rob flush MemBlock 566 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 567 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 568 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 569 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 570 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 571 // hybrid unit store data use this 572 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(isVector = true)))) 573 574 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 575 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 576 577 val tlbCsr = Output(new TlbCsrBundle) 578 val csrCtrl = Output(new CustomCSRCtrlIO) 579 val sfence = Output(new SfenceBundle) 580 val isStoreException = Output(Bool()) 581 582 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 583 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 584 Seq(issueLda(0)) ++ Seq(issueSta(0)) ++ 585 issueHylda ++ issueHysta ++ 586 Seq(issueLda(1)) ++ 587 issueVldu ++ 588 issueStd 589 } 590 591 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 592 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 593 Seq(writebackLda(0)) ++ Seq(writebackSta(0)) ++ 594 writebackHyuLda ++ writebackHyuSta ++ 595 Seq(writebackLda(1)) ++ 596 writebackVlda ++ 597 writebackStd 598 } 599} 600 601class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 602 val fromTop = new Bundle { 603 val hartId = Input(UInt(8.W)) 604 val externalInterrupt = new ExternalInterruptIO 605 } 606 607 val toTop = new Bundle { 608 val cpuHalted = Output(Bool()) 609 } 610 611 val fenceio = new FenceIO 612 // Todo: merge these bundles into BackendFrontendIO 613 val frontend = Flipped(new FrontendToCtrlIO) 614 val frontendSfence = Output(new SfenceBundle) 615 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 616 val frontendTlbCsr = Output(new TlbCsrBundle) 617 // distributed csr write 618 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 619 620 val mem = new BackendMemIO 621 622 val perf = Input(new PerfCounterIO) 623 624 val tlb = Output(new TlbCsrBundle) 625 626 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 627 628 val debugTopDown = new Bundle { 629 val fromRob = new RobCoreTopDownIO 630 val fromCore = new CoreDispatchTopDownIO 631 } 632 val debugRolling = new RobDebugRollingIO 633} 634