1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{PipelineConnect, ZeroExt} 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 10import xiangshan.backend.ctrlblock.CtrlBlock 11import xiangshan.backend.datapath.WbConfig._ 12import xiangshan.backend.datapath.{DataPath, WbDataPath} 13import xiangshan.backend.exu.ExuBlock 14import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 15import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, PerfCounterIO} 16import xiangshan.backend.issue.Scheduler 17import xiangshan.backend.rob.RobLsqIO 18import xiangshan.frontend.{FtqPtr, FtqRead} 19import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 20 21class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 22 with HasXSParameter { 23 24 for (exuCfg <- params.allExuParams) { 25 val fuConfigs = exuCfg.fuConfigs 26 val wbPortConfigs = exuCfg.wbPortConfigs 27 val immType = exuCfg.immType 28 println(s"exu: ${fuConfigs.map(_.name)}, wb: ${wbPortConfigs}, imm: ${immType}") 29 require(wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 30 fuConfigs.map(_.writeIntRf).reduce(_ || _), 31 "int wb port has no priority" ) 32 require(wbPortConfigs.collectFirst { case x: VecWB => x }.nonEmpty == 33 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 34 "vec wb port has no priority" ) 35 } 36 37 println(s"Function Unit: Alu(${params.AluCnt}), Brh(${params.BrhCnt}), Jmp(${params.JmpCnt}), " + 38 s"Ldu(${params.LduCnt}), Sta(${params.StaCnt}), Std(${params.StdCnt})") 39 40 val ctrlBlock = LazyModule(new CtrlBlock(params)) 41 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 42 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 43 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 44 val dataPath = LazyModule(new DataPath(params)) 45 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 46 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 47 48 lazy val module = new BackendImp(this) 49} 50 51class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 52 with HasXSParameter{ 53 implicit private val params = wrapper.params 54 val io = IO(new BackendIO()(p, wrapper.params)) 55 56 private val ctrlBlock = wrapper.ctrlBlock.module 57 private val intScheduler = wrapper.intScheduler.get.module 58 private val vfScheduler = wrapper.vfScheduler.get.module 59 private val memScheduler = wrapper.memScheduler.get.module 60 private val dataPath = wrapper.dataPath.module 61 private val intExuBlock = wrapper.intExuBlock.get.module 62 private val vfExuBlock = wrapper.vfExuBlock.get.module 63 private val wbDataPath = Module(new WbDataPath(params)) 64 65 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 66 ctrlBlock.io.frontend <> io.frontend 67 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 68 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 69 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 70 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 71 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 72 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 73 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 74 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 75 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 76 77 intScheduler.io.fromTop.hartId := io.fromTop.hartId 78 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 79 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 80 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 81 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 82 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 83 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 84 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 85 86 memScheduler.io.fromTop.hartId := io.fromTop.hartId 87 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 88 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 89 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 90 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 91 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 92 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 93 memScheduler.io.fromMem.get.lcommit := ctrlBlock.io.robio.lsq.lcommit 94 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 95 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 96 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 97 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 98 sink.valid := source.valid 99 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 100 sink.bits.uop.robIdx := source.bits.robIdx 101 } 102 103 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 104 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 105 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 106 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 107 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 108 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 109 110 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 111 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 112 val vconfig = dataPath.io.vconfigReadPort.data 113 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 114 for (i <- 0 until dataPath.io.fromIntIQ.length) { 115 for (j <- 0 until dataPath.io.fromIntIQ(i).length) { 116 PipelineConnect(intScheduler.io.toDataPath(i)(j), dataPath.io.fromIntIQ(i)(j), dataPath.io.fromIntIQ(i)(j).valid, 117 intScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush)) 118 intScheduler.io.fromDataPath(i)(j) := dataPath.io.toIntIQ(i)(j) 119 } 120 } 121 122 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPath 123 vfScheduler.io.fromDataPath := dataPath.io.toVfIQ 124 dataPath.io.fromMemIQ <> memScheduler.io.toDataPath 125 memScheduler.io.fromDataPath := dataPath.io.toMemIQ 126 127 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 128 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 129 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 130 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 131 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 132 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 133 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 134 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 135 136 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 137 for (i <- 0 until intExuBlock.io.in.length) { 138 for (j <- 0 until intExuBlock.io.in(i).length) { 139 PipelineConnect(dataPath.io.toIntExu(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 140 Mux(dataPath.io.toIntExu(i)(j).fire, 141 dataPath.io.toIntExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 142 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 143 } 144 } 145 146 private val csrio = intExuBlock.io.csrio.get 147 csrio.hartId := io.fromTop.hartId 148 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 149 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 150 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 151 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 152 csrio.fpu.isIllegal := false.B // Todo: remove it 153 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 154 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 155 156 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 157 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 158 val debugVl = debugVconfig.vl 159 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 160 csrio.vpu.set_vstart.bits := 0.U 161 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 162 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 163 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 164 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 165 csrio.exception := ctrlBlock.io.robio.exception 166 csrio.memExceptionVAddr := io.mem.exceptionVAddr 167 csrio.externalInterrupt := io.fromTop.externalInterrupt 168 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 169 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 170 csrio.perf <> io.perf 171 private val fenceio = intExuBlock.io.fenceio.get 172 fenceio.disableSfence := csrio.disableSfence 173 io.fenceio <> fenceio 174 175 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 176 for (i <- 0 until vfExuBlock.io.in.size) { 177 for (j <- 0 until vfExuBlock.io.in(i).size) { 178 PipelineConnect(dataPath.io.toFpExu(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 179 Mux(dataPath.io.toFpExu(i)(j).fire, 180 dataPath.io.toFpExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 181 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 182 } 183 } 184 vfExuBlock.io.frm.get := csrio.fpu.frm 185 186 wbDataPath.io.flush := ctrlBlock.io.redirect 187 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 188 wbDataPath.io.fromIntExu <> intExuBlock.io.out 189 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 190 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 191 sink.valid := source.valid 192 source.ready := sink.ready 193 sink.bits.data := source.bits.data 194 sink.bits.pdest := source.bits.uop.pdest 195 sink.bits.robIdx := source.bits.uop.robIdx 196 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 197 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 198 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 199 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 200 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 201 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 202 sink.bits.debug := source.bits.debug 203 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 204 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 205 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 206 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 207 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 208 } 209 210 // to mem 211 io.mem.redirect := ctrlBlock.io.redirect 212 io.mem.issueUops.zip(dataPath.io.toMemExu.flatten).foreach { case (sink, source) => 213 sink.valid := source.valid 214 source.ready := sink.ready 215 sink.bits.iqIdx := source.bits.iqIdx 216 sink.bits.isFirstIssue := source.bits.isFirstIssue 217 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 218 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 219 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 220 sink.bits.uop.fuType := source.bits.fuType 221 sink.bits.uop.fuOpType := source.bits.fuOpType 222 sink.bits.uop.imm := source.bits.imm 223 sink.bits.uop.robIdx := source.bits.robIdx 224 sink.bits.uop.pdest := source.bits.pdest 225 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 226 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 227 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 228 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 229 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 230 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 231 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 232 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 233 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 234 } 235 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 236 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 237 io.mem.tlbCsr := csrio.tlb 238 io.mem.csrCtrl := csrio.customCtrl 239 io.mem.sfence := fenceio.sfence 240 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 241 require(io.mem.loadPcRead.size == params.LduCnt) 242 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 243 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 244 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 245 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 246 } 247 // mem io 248 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 249 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 250 io.mem.toSbuffer <> fenceio.sbuffer 251 io.mem.rsFeedBack <> memScheduler.io.memIO.get.feedbackIO 252 253 io.frontendSfence := fenceio.sfence 254 io.frontendTlbCsr := csrio.tlb 255 io.frontendCsrCtrl := csrio.customCtrl 256 257 io.tlb <> csrio.tlb 258 259 io.csrCustomCtrl := csrio.customCtrl 260 261 dontTouch(memScheduler.io) 262 dontTouch(io.mem) 263 dontTouch(dataPath.io.toMemExu) 264 dontTouch(wbDataPath.io.fromMemExu) 265} 266 267class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 268 // In/Out // Todo: split it into one-direction bundle 269 val lsqEnqIO = Flipped(new LsqEnqIO) 270 val robLsqIO = new RobLsqIO 271 val toSbuffer = new FenceToSbuffer 272 val rsFeedBack = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 273 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 274 275 // Input 276 val writeBack = Vec(params.LduCnt + params.StaCnt * 2, Flipped(DecoupledIO(new MemExuOutput()))) 277 278 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 279 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 280 val memoryViolation = Flipped(ValidIO(new Redirect)) 281 val exceptionVAddr = Input(UInt(VAddrBits.W)) 282 val sqDeq = Input(UInt(params.StaCnt.W)) 283 284 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 285 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 286 287 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 288 val stIssuePtr = Input(new SqPtr()) 289 290 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 291 292 // Output 293 val redirect = ValidIO(new Redirect) // rob flush MemBlock 294 val issueUops = Vec(params.LduCnt + 2 * params.StaCnt, DecoupledIO(new MemExuInput())) 295 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 296 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 297 298 val tlbCsr = Output(new TlbCsrBundle) 299 val csrCtrl = Output(new CustomCSRCtrlIO) 300 val sfence = Output(new SfenceBundle) 301 val isStoreException = Output(Bool()) 302} 303 304class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 305 val fromTop = new Bundle { 306 val hartId = Input(UInt(8.W)) 307 val externalInterrupt = new ExternalInterruptIO 308 } 309 310 val toTop = new Bundle { 311 val cpuHalted = Output(Bool()) 312 } 313 314 val fenceio = new FenceIO 315 // Todo: merge these bundles into BackendFrontendIO 316 val frontend = Flipped(new FrontendToCtrlIO) 317 val frontendSfence = Output(new SfenceBundle) 318 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 319 val frontendTlbCsr = Output(new TlbCsrBundle) 320 // distributed csr write 321 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 322 323 val mem = new BackendMemIO 324 325 val perf = Input(new PerfCounterIO) 326 327 val tlb = Output(new TlbCsrBundle) 328 329 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 330} 331