1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 10import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 11import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 12import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 13import xiangshan.backend.datapath.WbConfig._ 14import xiangshan.backend.datapath._ 15import xiangshan.backend.dispatch.CoreDispatchTopDownIO 16import xiangshan.backend.exu.ExuBlock 17import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 18import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 19import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 20import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO} 21import xiangshan.frontend.{FtqPtr, FtqRead} 22import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 23 24class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 25 with HasXSParameter { 26 27 override def shouldBeInlined: Boolean = false 28 29 /* Only update the idx in mem-scheduler here 30 * Idx in other schedulers can be updated the same way if needed 31 * 32 * Also note that we filter out the 'stData issue-queues' when counting 33 */ 34 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 35 ibp.updateIdx(idx) 36 } 37 38 println(params.iqWakeUpParams) 39 40 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 41 schdCfg.bindBackendParam(params) 42 } 43 44 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 45 iqCfg.bindBackendParam(params) 46 } 47 48 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 49 exuCfg.bindBackendParam(params) 50 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 51 exuCfg.updateExuIdx(i) 52 } 53 54 println("[Backend] ExuConfigs:") 55 for (exuCfg <- params.allExuParams) { 56 val fuConfigs = exuCfg.fuConfigs 57 val wbPortConfigs = exuCfg.wbPortConfigs 58 val immType = exuCfg.immType 59 60 println("[Backend] " + 61 s"${exuCfg.name}: " + 62 (if (exuCfg.fakeUnit) "fake, " else "") + 63 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 64 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 65 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 66 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 67 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 68 s"srcReg(${exuCfg.numRegSrc})" 69 ) 70 require( 71 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 72 fuConfigs.map(_.writeIntRf).reduce(_ || _), 73 "int wb port has no priority" 74 ) 75 require( 76 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 77 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 78 "vec wb port has no priority" 79 ) 80 } 81 82 println(s"[Backend] all fu configs") 83 for (cfg <- FuConfig.allConfigs) { 84 println(s"[Backend] $cfg") 85 } 86 87 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 88 for ((port, seq) <- params.getRdPortParams(IntData())) { 89 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 90 } 91 92 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 93 for ((port, seq) <- params.getWbPortParams(IntData())) { 94 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 95 } 96 97 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 98 for ((port, seq) <- params.getRdPortParams(VecData())) { 99 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 100 } 101 102 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 103 for ((port, seq) <- params.getWbPortParams(VecData())) { 104 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 105 } 106 107 val ctrlBlock = LazyModule(new CtrlBlock(params)) 108 val pcTargetMem = LazyModule(new PcTargetMem(params)) 109 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 110 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 111 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 112 val cancelNetwork = LazyModule(new CancelNetwork(params)) 113 val dataPath = LazyModule(new DataPath(params)) 114 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 115 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 116 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 117 118 lazy val module = new BackendImp(this) 119} 120 121class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 122 with HasXSParameter { 123 implicit private val params = wrapper.params 124 125 val io = IO(new BackendIO()(p, wrapper.params)) 126 127 private val ctrlBlock = wrapper.ctrlBlock.module 128 private val pcTargetMem = wrapper.pcTargetMem.module 129 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 130 private val vfScheduler = wrapper.vfScheduler.get.module 131 private val memScheduler = wrapper.memScheduler.get.module 132 private val cancelNetwork = wrapper.cancelNetwork.module 133 private val dataPath = wrapper.dataPath.module 134 private val intExuBlock = wrapper.intExuBlock.get.module 135 private val vfExuBlock = wrapper.vfExuBlock.get.module 136 private val bypassNetwork = Module(new BypassNetwork) 137 private val wbDataPath = Module(new WbDataPath(params)) 138 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 139 140 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 141 intScheduler.io.toSchedulers.wakeupVec ++ 142 vfScheduler.io.toSchedulers.wakeupVec ++ 143 memScheduler.io.toSchedulers.wakeupVec 144 ).map(x => (x.bits.exuIdx, x)).toMap 145 146 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 147 148 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 149 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 150 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 151 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 152 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 153 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 154 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 155 156 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 157 158 private val vconfig = dataPath.io.vconfigReadPort.data 159 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 160 private val og0CancelOHFromDataPath: UInt = dataPath.io.og0CancelOH 161 private val og0CancelOHFromCancelNet: UInt = cancelNetwork.io.out.og0CancelOH 162 private val og0CancelOHFromFinalIssue: UInt = Wire(chiselTypeOf(dataPath.io.og0CancelOH)) 163 private val og0CancelOH: UInt = og0CancelOHFromDataPath | og0CancelOHFromCancelNet | og0CancelOHFromFinalIssue 164 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 165 166 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 167 ctrlBlock.io.frontend <> io.frontend 168 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 169 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 170 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 171 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 172 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 173 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 174 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 175 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 176 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 177 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 178 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 179 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 180 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 181 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 182 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 183 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 184 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 185 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 186 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 187 188 189 intScheduler.io.fromTop.hartId := io.fromTop.hartId 190 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 191 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 192 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 193 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 194 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 195 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 196 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 197 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 198 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 199 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 200 intScheduler.io.ldCancel := io.mem.ldCancel 201 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 202 203 memScheduler.io.fromTop.hartId := io.fromTop.hartId 204 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 205 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 206 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 207 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 208 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 209 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 210 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 211 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 212 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 213 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 214 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 215 sink.valid := source.valid 216 sink.bits := source.bits.robIdx 217 } 218 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 219 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 220 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 221 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 222 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 223 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 224 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 225 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 226 memScheduler.io.ldCancel := io.mem.ldCancel 227 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 228 229 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 230 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 231 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 232 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 233 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 234 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 235 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 236 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 237 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 238 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 239 vfScheduler.io.ldCancel := io.mem.ldCancel 240 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 241 242 cancelNetwork.io.in.int <> intScheduler.io.toDataPath 243 cancelNetwork.io.in.vf <> vfScheduler.io.toDataPath 244 cancelNetwork.io.in.mem <> memScheduler.io.toDataPath 245 cancelNetwork.io.in.og0CancelOH := og0CancelOHFromDataPath | og0CancelOHFromFinalIssue 246 cancelNetwork.io.in.og1CancelOH := og1CancelOH 247 intScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.int 248 vfScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.vf 249 memScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.mem 250 251 dataPath.io.hartId := io.fromTop.hartId 252 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 253 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 254 255 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 256 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 257 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 258 259 dataPath.io.ldCancel := io.mem.ldCancel 260 261 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 262 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 263 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 264 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 265 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 266 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 267 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 268 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 269 270 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 271 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 272 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 273 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 274 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 275 276 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 277 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 278 s"io.mem.writeback(${io.mem.writeBack.size})" 279 ) 280 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 281 sink.valid := source.valid 282 sink.bits.pdest := source.bits.uop.pdest 283 sink.bits.data := source.bits.data 284 } 285 286 287 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 288 for (i <- 0 until intExuBlock.io.in.length) { 289 for (j <- 0 until intExuBlock.io.in(i).length) { 290 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 291 NewPipelineConnect( 292 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 293 Mux( 294 bypassNetwork.io.toExus.int(i)(j).fire, 295 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 296 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 297 ) 298 ) 299 } 300 } 301 302 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 303 pcTargetMem.io.fromDataPathFtq := bypassNetwork.io.toExus.int.flatten.filter(_.bits.params.hasPredecode).map(_.bits.ftqIdx.get).toSeq 304 intExuBlock.io.in.flatten.filter(_.bits.params.hasPredecode).map(_.bits.predictInfo.get.target).zipWithIndex.foreach { 305 case (sink, i) => 306 sink := pcTargetMem.io.toExus(i) 307 } 308 309 private val csrio = intExuBlock.io.csrio.get 310 csrio.hartId := io.fromTop.hartId 311 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 312 csrio.fpu.isIllegal := false.B // Todo: remove it 313 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 314 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 315 316 val debugVconfig = dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 317 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 318 val debugVl = debugVconfig.vl 319 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 320 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 321 csrio.vpu.set_vstart.bits := 0.U 322 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 323 //Todo here need change design 324 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 325 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 326 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 327 csrio.exception := ctrlBlock.io.robio.exception 328 csrio.memExceptionVAddr := io.mem.exceptionVAddr 329 csrio.externalInterrupt := io.fromTop.externalInterrupt 330 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 331 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 332 csrio.perf <> io.perf 333 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 334 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 335 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 336 private val fenceio = intExuBlock.io.fenceio.get 337 io.fenceio <> fenceio 338 fenceio.disableSfence := csrio.disableSfence 339 340 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 341 for (i <- 0 until vfExuBlock.io.in.size) { 342 for (j <- 0 until vfExuBlock.io.in(i).size) { 343 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 344 NewPipelineConnect( 345 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 346 Mux( 347 bypassNetwork.io.toExus.vf(i)(j).fire, 348 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 349 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 350 ) 351 ) 352 353 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 354 } 355 } 356 357 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 358 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 359 360 wbDataPath.io.flush := ctrlBlock.io.redirect 361 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 362 wbDataPath.io.fromIntExu <> intExuBlock.io.out 363 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 364 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 365 sink.valid := source.valid 366 source.ready := sink.ready 367 sink.bits.data := source.bits.data 368 sink.bits.pdest := source.bits.uop.pdest 369 sink.bits.robIdx := source.bits.uop.robIdx 370 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 371 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 372 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 373 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 374 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 375 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 376 sink.bits.debug := source.bits.debug 377 sink.bits.debugInfo := source.bits.uop.debugInfo 378 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 379 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 380 } 381 382 // to mem 383 private val memIssueParams = params.memSchdParams.get.issueBlockParams 384 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 385 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 386 387 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 388 for (i <- toMem.indices) { 389 for (j <- toMem(i).indices) { 390 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 391 val issueTimeout = 392 if (memExuBlocksHasLDU(i)(j)) 393 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 394 else 395 false.B 396 397 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 398 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 399 memScheduler.io.loadFinalIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 400 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 401 memScheduler.io.loadFinalIssueResp(i)(j).bits.respType := RSFeedbackType.fuBusy 402 memScheduler.io.loadFinalIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 403 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 404 } 405 406 NewPipelineConnect( 407 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 408 Mux( 409 bypassNetwork.io.toExus.mem(i)(j).fire, 410 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 411 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 412 ) 413 ) 414 415 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 416 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 417 memScheduler.io.memAddrIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 418 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 419 memScheduler.io.memAddrIssueResp(i)(j).bits.respType := RSFeedbackType.fuIdle 420 memScheduler.io.memAddrIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 421 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 422 } 423 } 424 } 425 426 io.mem.redirect := ctrlBlock.io.redirect 427 private val memIssueUops = 428 Seq(io.mem.issueLda(0)) ++ Seq(io.mem.issueSta(0)) ++ 429 io.mem.issueHylda ++ io.mem.issueHysta ++ 430 Seq(io.mem.issueLda(1)) ++ 431 io.mem.issueVldu ++ 432 io.mem.issueStd 433 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 434 sink.valid := source.valid 435 source.ready := sink.ready 436 sink.bits.iqIdx := source.bits.iqIdx 437 sink.bits.isFirstIssue := source.bits.isFirstIssue 438 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 439 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 440 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 441 sink.bits.deqPortIdx := source.bits.deqLdExuIdx.getOrElse(0.U) 442 sink.bits.uop.fuType := source.bits.fuType 443 sink.bits.uop.fuOpType := source.bits.fuOpType 444 sink.bits.uop.imm := source.bits.imm 445 sink.bits.uop.robIdx := source.bits.robIdx 446 sink.bits.uop.pdest := source.bits.pdest 447 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 448 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 449 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 450 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 451 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 452 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 453 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 454 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 455 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 456 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 457 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 458 } 459 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 460 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 461 io.mem.tlbCsr := csrio.tlb 462 io.mem.csrCtrl := csrio.customCtrl 463 io.mem.sfence := fenceio.sfence 464 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 465 require(io.mem.loadPcRead.size == params.LduCnt) 466 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 467 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 468 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 469 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 470 require(toMem.head(i).bits.ftqIdx.isDefined && toMem.head(i).bits.ftqOffset.isDefined) 471 } 472 473 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 474 storePcRead := ctrlBlock.io.memStPcRead(i).data 475 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 476 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 477 require(toMem(1)(i).bits.ftqIdx.isDefined && toMem(1)(i).bits.ftqOffset.isDefined) 478 } 479 480 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 481 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 482 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 483 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 484 require(toMem(2)(i).bits.ftqIdx.isDefined && toMem(2)(i).bits.ftqOffset.isDefined) 485 }) 486 487 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 488 489 // mem io 490 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 491 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 492 493 private val intFinalIssueBlock = intExuBlock.io.in.flatten.toSeq.map(_ => false.B) 494 private val vfFinalIssueBlock = vfExuBlock.io.in.flatten.toSeq.map(_ => false.B) 495 private val memFinalIssueBlock = io.mem.issueUops.toSeq zip memExuBlocksHasLDU.flatten.toSeq map { 496 case (out, true) => RegNext(out.valid && !out.ready, false.B) 497 case (_, false) => false.B 498 } 499 println(s"[backend]: width of [int|vf|mem]FinalIssueBlock: ${intFinalIssueBlock.size}|${vfFinalIssueBlock.size}|${memFinalIssueBlock.size}") 500 og0CancelOHFromFinalIssue := VecInit(intFinalIssueBlock ++ vfFinalIssueBlock ++ memFinalIssueBlock).asUInt 501 502 io.frontendSfence := fenceio.sfence 503 io.frontendTlbCsr := csrio.tlb 504 io.frontendCsrCtrl := csrio.customCtrl 505 506 io.tlb <> csrio.tlb 507 508 io.csrCustomCtrl := csrio.customCtrl 509 510 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 511 512 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 513 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 514 515 io.debugRolling := ctrlBlock.io.debugRolling 516 517 dontTouch(memScheduler.io) 518 dontTouch(dataPath.io.toMemExu) 519 dontTouch(wbDataPath.io.fromMemExu) 520} 521 522class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 523 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 524 val flippedLda = true 525 // params alias 526 private val LoadQueueSize = VirtualLoadQueueSize 527 // In/Out // Todo: split it into one-direction bundle 528 val lsqEnqIO = Flipped(new LsqEnqIO) 529 val robLsqIO = new RobLsqIO 530 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 531 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 532 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 533 val ldCancel = Vec(params.LduCnt + params.HyuCnt, Flipped(new LoadCancelIO)) 534 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 535 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 536 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 537 // Input 538 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 539 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 540 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 541 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 542 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 543 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 544 545 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 546 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 547 val memoryViolation = Flipped(ValidIO(new Redirect)) 548 val exceptionVAddr = Input(UInt(VAddrBits.W)) 549 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 550 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 551 552 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 553 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 554 555 val lqCanAccept = Input(Bool()) 556 val sqCanAccept = Input(Bool()) 557 558 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 559 val stIssuePtr = Input(new SqPtr()) 560 561 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 562 563 val debugLS = Flipped(Output(new DebugLSIO)) 564 565 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 566 // Output 567 val redirect = ValidIO(new Redirect) // rob flush MemBlock 568 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 569 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 570 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 571 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 572 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 573 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 574 575 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 576 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 577 578 val tlbCsr = Output(new TlbCsrBundle) 579 val csrCtrl = Output(new CustomCSRCtrlIO) 580 val sfence = Output(new SfenceBundle) 581 val isStoreException = Output(Bool()) 582 583 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 584 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 585 Seq(issueLda(0)) ++ Seq(issueSta(0)) ++ 586 issueHylda ++ issueHysta ++ 587 Seq(issueLda(1)) ++ 588 issueVldu ++ 589 issueStd 590 } 591 592 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 593 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 594 Seq(writebackLda(0)) ++ Seq(writebackSta(0)) ++ 595 writebackHyuLda ++ writebackHyuSta ++ 596 Seq(writebackLda(1)) ++ 597 writebackVldu ++ 598 writebackStd 599 } 600} 601 602class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 603 val fromTop = new Bundle { 604 val hartId = Input(UInt(8.W)) 605 val externalInterrupt = new ExternalInterruptIO 606 } 607 608 val toTop = new Bundle { 609 val cpuHalted = Output(Bool()) 610 } 611 612 val fenceio = new FenceIO 613 // Todo: merge these bundles into BackendFrontendIO 614 val frontend = Flipped(new FrontendToCtrlIO) 615 val frontendSfence = Output(new SfenceBundle) 616 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 617 val frontendTlbCsr = Output(new TlbCsrBundle) 618 // distributed csr write 619 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 620 621 val mem = new BackendMemIO 622 623 val perf = Input(new PerfCounterIO) 624 625 val tlb = Output(new TlbCsrBundle) 626 627 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 628 629 val debugTopDown = new Bundle { 630 val fromRob = new RobCoreTopDownIO 631 val fromCore = new CoreDispatchTopDownIO 632 } 633 val debugRolling = new RobDebugRollingIO 634} 635