xref: /XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala (revision dd980d61d112e35067e0af32f17938e2700612c5)
16f483f86SXuan Hupackage xiangshan.backend
26f483f86SXuan Hu
36f483f86SXuan Huimport chisel3._
46f483f86SXuan Huimport chisel3.util._
56f483f86SXuan Huimport freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
66f483f86SXuan Huimport org.chipsalliance.cde.config.Parameters
76f483f86SXuan Huimport utility.SyncDataModuleTemplate
86f483f86SXuan Huimport xiangshan.HasXSParameter
96f483f86SXuan Huimport xiangshan.frontend.{FtqPtr, IfuToBackendIO}
106f483f86SXuan Hu
116f483f86SXuan Huclass GPAMem(implicit p: Parameters) extends LazyModule {
126f483f86SXuan Hu  override def shouldBeInlined: Boolean = false
136f483f86SXuan Hu
146f483f86SXuan Hu  lazy val module = new GPAMemImp(this)
156f483f86SXuan Hu}
166f483f86SXuan Hu
176f483f86SXuan Huclass GPAMemImp(override val wrapper: GPAMem)(implicit p: Parameters) extends LazyModuleImp(wrapper) with HasXSParameter {
186f483f86SXuan Hu  val io = IO(new GPAMemIO)
196f483f86SXuan Hu
20ad415ae0SXiaokun-Pei  private val mem = Module (new SyncDataModuleTemplate(new GPAMemEntry, FtqSize, numRead = 1, numWrite = 1, hasRen = true))
216f483f86SXuan Hu
226f483f86SXuan Hu  mem.io.wen.head := io.fromIFU.gpaddrMem_wen
236f483f86SXuan Hu  mem.io.waddr.head := io.fromIFU.gpaddrMem_waddr
246f483f86SXuan Hu  mem.io.wdata.head := io.fromIFU.gpaddrMem_wdata
256f483f86SXuan Hu
266f483f86SXuan Hu  mem.io.ren.get.head := io.exceptionReadAddr.valid
276f483f86SXuan Hu  mem.io.raddr.head := io.exceptionReadAddr.bits.ftqPtr.value
286f483f86SXuan Hu
296f483f86SXuan Hu  private val ftqOffset = RegEnable(io.exceptionReadAddr.bits.ftqOffset, io.exceptionReadAddr.valid)
306f483f86SXuan Hu
31ad415ae0SXiaokun-Pei  private val gpabase = mem.io.rdata.head.gpaddr
323adc7007STang Haojin  private val gpa = gpabase + Cat(ftqOffset, 0.U(instOffsetBits.W))
336f483f86SXuan Hu
34ad415ae0SXiaokun-Pei  io.exceptionReadData.gpaddr := gpa
35ad415ae0SXiaokun-Pei  io.exceptionReadData.isForVSnonLeafPTE := mem.io.rdata.head.isForVSnonLeafPTE
366f483f86SXuan Hu
376f483f86SXuan Hu  def getGPAPage(vaddr: UInt): UInt = {
386f483f86SXuan Hu    require(vaddr.getWidth == GPAddrBits, s"The width of gpa should be $GPAddrBits")
396f483f86SXuan Hu    vaddr(GPAddrBits - 1, PageOffsetWidth)
406f483f86SXuan Hu  }
416f483f86SXuan Hu}
426f483f86SXuan Hu
43ad415ae0SXiaokun-Peiclass GPAMemEntry(implicit val p: Parameters) extends Bundle with HasXSParameter {
44*dd980d61SXu, Zefan  val gpaddr = UInt(PAddrBitsMax.W)
45ad415ae0SXiaokun-Pei  val isForVSnonLeafPTE = Bool()
46ad415ae0SXiaokun-Pei}
47ad415ae0SXiaokun-Pei
486f483f86SXuan Huclass GPAMemIO(implicit val p: Parameters) extends Bundle with HasXSParameter {
496f483f86SXuan Hu  val fromIFU = Flipped(new IfuToBackendIO())
506f483f86SXuan Hu
516f483f86SXuan Hu  val exceptionReadAddr = Input(ValidIO(new Bundle {
526f483f86SXuan Hu    val ftqPtr = new FtqPtr()
536f483f86SXuan Hu    val ftqOffset = UInt(log2Up(PredictWidth).W)
546f483f86SXuan Hu  }))
55ad415ae0SXiaokun-Pei  val exceptionReadData = Output(new GPAMemEntry)
566f483f86SXuan Hu}
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