1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3.Output 5import chisel3.util.{DecoupledIO, MixedVec, ValidIO, log2Up} 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.WriteBackBundle 8import xiangshan.backend.datapath.DataConfig._ 9import xiangshan.backend.datapath.WbConfig._ 10import xiangshan.backend.regfile.PregParams 11 12case class WbArbiterParams( 13 wbCfgs : Seq[PregWB], 14 pregParams: PregParams, 15 backendParams: BackendParams, 16) { 17 18 def numIn = wbCfgs.length 19 20 def numOut = wbCfgs.head match { 21 case _: WbConfig.IntWB => pregParams.numWrite.getOrElse(backendParams.getWbPortIndices(IntData()).size) 22 case _: WbConfig.FpWB => pregParams.numWrite.getOrElse(backendParams.getWbPortIndices(FpData()).size) 23 case _: WbConfig.VfWB => pregParams.numWrite.getOrElse(backendParams.getWbPortIndices(VecData()).size) 24 case _: WbConfig.V0WB => pregParams.numWrite.getOrElse(backendParams.getWbPortIndices(V0Data()).size) 25 case _: WbConfig.VlWB => pregParams.numWrite.getOrElse(backendParams.getWbPortIndices(VlData()).size) 26 case x => 27 assert(assertion = false, s"the WbConfig in WbArbiterParams should be either IntWB or FpWB or VfWB or V0WB or VlWB, found ${x.getClass}") 28 0 29 } 30 31 def dataWidth = pregParams.dataCfg.dataWidth 32 33 def addrWidth = log2Up(pregParams.numEntries) 34 35 def genInput(implicit p: Parameters) = { 36 MixedVec(wbCfgs.map(x => DecoupledIO(new WriteBackBundle(x, backendParams)))) 37 } 38 39 def genOutput(implicit p: Parameters): MixedVec[ValidIO[WriteBackBundle]] = { 40 Output(MixedVec(Seq.tabulate(numOut) { 41 x => 42 ValidIO(new WriteBackBundle( 43 wbCfgs.head.dataCfg match { 44 case IntData() => IntWB(port = x) 45 case FpData() => FpWB(port = x) 46 case VecData() => VfWB(port = x) 47 case V0Data() => V0WB(port = x) 48 case VlData() => VlWB(port = x) 49 case _ => ??? 50 }, 51 backendParams 52 ) 53 ) 54 } 55 ) 56 ) 57 } 58} 59