1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import freechips.rocketchip.rocket.Instructions._ 29 30/** 31 * Abstract trait giving defaults and other relevant values to different Decode constants/ 32 */ 33abstract trait DecodeConstants { 34 // This X should be used only in 1-bit signal. Otherwise, use BitPat("b???") to align with the width of UInt. 35 def X = BitPat("b0") 36 def N = BitPat("b0") 37 def Y = BitPat("b1") 38 def T = true 39 def F = false 40 41 def decodeDefault: List[BitPat] = // illegal instruction 42 // srcType(0) srcType(1) srcType(2) fuType fuOpType rfWen 43 // | | | | | | fpWen 44 // | | | | | | | vecWen 45 // | | | | | | | | isXSTrap 46 // | | | | | | | | | noSpecExec 47 // | | | | | | | | | | blockBackward 48 // | | | | | | | | | | | flushPipe 49 // | | | | | | | | | | | | selImm 50 List(SrcType.X, SrcType.X, SrcType.X, FuType.X, FuOpType.X, N, N, N, N, N, N, N, SelImm.INVALID_INSTR) // Use SelImm to indicate invalid instr 51 52 val decodeArray: Array[(BitPat, XSDecodeBase)] 53 final def table: Array[(BitPat, List[BitPat])] = decodeArray.map(x => (x._1, x._2.generate())) 54} 55 56trait DecodeUnitConstants 57{ 58 // abstract out instruction decode magic numbers 59 val RD_MSB = 11 60 val RD_LSB = 7 61 val RS1_MSB = 19 62 val RS1_LSB = 15 63 val RS2_MSB = 24 64 val RS2_LSB = 20 65 val RS3_MSB = 31 66 val RS3_LSB = 27 67} 68 69/** 70 * Decoded control signals 71 * See xiangshan/package.scala, xiangshan/backend/package.scala, Bundle.scala 72 */ 73 74abstract class XSDecodeBase { 75 def X = BitPat("b?") 76 def N = BitPat("b0") 77 def Y = BitPat("b1") 78 def T = true 79 def F = false 80 def generate() : List[BitPat] 81} 82 83case class XSDecode( 84 src1: BitPat, src2: BitPat, src3: BitPat, 85 fu: BitPat, fuOp: BitPat, selImm: BitPat, 86 xWen: Boolean = false, 87 fWen: Boolean = false, 88 vWen: Boolean = false, 89 mWen: Boolean = false, 90 xsTrap: Boolean = false, 91 noSpec: Boolean = false, 92 blockBack: Boolean = false, 93 flushPipe: Boolean = false, 94) extends XSDecodeBase { 95 def generate() : List[BitPat] = { 96 List (src1, src2, src3, fu, fuOp, xWen.B, fWen.B, (vWen || mWen).B, xsTrap.B, noSpec.B, blockBack.B, flushPipe.B, selImm) 97 } 98} 99 100case class FDecode( 101 src1: BitPat, src2: BitPat, src3: BitPat, 102 fu: BitPat, fuOp: BitPat, selImm: BitPat = SelImm.X, 103 xWen: Boolean = false, 104 fWen: Boolean = false, 105 vWen: Boolean = false, 106 mWen: Boolean = false, 107 xsTrap: Boolean = false, 108 noSpec: Boolean = false, 109 blockBack: Boolean = false, 110 flushPipe: Boolean = false, 111) extends XSDecodeBase { 112 def generate() : List[BitPat] = { 113 XSDecode(src1, src2, src3, fu, fuOp, selImm, xWen, fWen, vWen, mWen, xsTrap, noSpec, blockBack, flushPipe).generate() 114 } 115} 116 117/** 118 * Decode constants for RV64 119 */ 120object X64Decode extends DecodeConstants { 121 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 122 LD -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld , SelImm.IMM_I, xWen = T), 123 LWU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lwu , SelImm.IMM_I, xWen = T), 124 SD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sd , SelImm.IMM_S ), 125 126 SLLI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sll , SelImm.IMM_I, xWen = T), 127 SRLI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srl , SelImm.IMM_I, xWen = T), 128 SRAI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sra , SelImm.IMM_I, xWen = T), 129 130 ADDIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.addw, SelImm.IMM_I, xWen = T), 131 SLLIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sllw, SelImm.IMM_I, xWen = T), 132 SRAIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sraw, SelImm.IMM_I, xWen = T), 133 SRLIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srlw, SelImm.IMM_I, xWen = T), 134 135 ADDW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.addw, SelImm.X , xWen = T), 136 SUBW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.subw, SelImm.X , xWen = T), 137 SLLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sllw, SelImm.X , xWen = T), 138 SRAW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sraw, SelImm.X , xWen = T), 139 SRLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srlw, SelImm.X , xWen = T), 140 141 RORW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rorw, SelImm.X , xWen = T), 142 RORIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.rorw, SelImm.IMM_I, xWen = T), 143 ROLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rolw, SelImm.X , xWen = T), 144 ) 145} 146 147/** 148 * Overall Decode constants 149 */ 150object XDecode extends DecodeConstants { 151 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 152 LW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw , SelImm.IMM_I, xWen = T), 153 LH -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lh , SelImm.IMM_I, xWen = T), 154 LHU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lhu , SelImm.IMM_I, xWen = T), 155 LB -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lb , SelImm.IMM_I, xWen = T), 156 LBU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lbu , SelImm.IMM_I, xWen = T), 157 SW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sw , SelImm.IMM_S ), 158 SH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sh , SelImm.IMM_S ), 159 SB -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sb , SelImm.IMM_S ), 160 LUI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add , SelImm.IMM_U, xWen = T), 161 ADDI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add , SelImm.IMM_I, xWen = T), 162 ANDI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.and , SelImm.IMM_I, xWen = T), 163 ORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.or , SelImm.IMM_I, xWen = T), 164 XORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.xor , SelImm.IMM_I, xWen = T), 165 SLTI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slt , SelImm.IMM_I, xWen = T), 166 SLTIU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sltu, SelImm.IMM_I, xWen = T), 167 SLL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sll , SelImm.X , xWen = T), 168 ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.add , SelImm.X , xWen = T), 169 SUB -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sub , SelImm.X , xWen = T), 170 SLT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.slt , SelImm.X , xWen = T), 171 SLTU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sltu, SelImm.X , xWen = T), 172 AND -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.and , SelImm.X , xWen = T), 173 OR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.or , SelImm.X , xWen = T), 174 XOR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xor , SelImm.X , xWen = T), 175 SRA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sra , SelImm.X , xWen = T), 176 SRL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srl , SelImm.X , xWen = T), 177 178 MUL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mul , SelImm.X, xWen = T), 179 MULH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulh , SelImm.X, xWen = T), 180 MULHU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhu , SelImm.X, xWen = T), 181 MULHSU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhsu, SelImm.X, xWen = T), 182 MULW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulw , SelImm.X, xWen = T), 183 184 DIV -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.div , SelImm.X, xWen = T), 185 DIVU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divu , SelImm.X, xWen = T), 186 REM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.rem , SelImm.X, xWen = T), 187 REMU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remu , SelImm.X, xWen = T), 188 DIVW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divw , SelImm.X, xWen = T), 189 DIVUW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divuw , SelImm.X, xWen = T), 190 REMW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remw , SelImm.X, xWen = T), 191 REMUW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remuw , SelImm.X, xWen = T), 192 193 AUIPC -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.auipc, SelImm.IMM_U , xWen = T), 194 JAL -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jal , SelImm.IMM_UJ, xWen = T), 195 JALR -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jalr , SelImm.IMM_I , xWen = T), 196 BEQ -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.beq , SelImm.IMM_SB ), 197 BNE -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bne , SelImm.IMM_SB ), 198 BGE -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bge , SelImm.IMM_SB ), 199 BGEU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bgeu , SelImm.IMM_SB ), 200 BLT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.blt , SelImm.IMM_SB ), 201 BLTU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bltu , SelImm.IMM_SB ), 202 203 // I-type, XSDecodeiate12 holds the CSR register. 204 CSRRW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrt , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 205 CSRRS -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.set , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 206 CSRRC -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clr , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 207 208 CSRRWI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrti, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 209 CSRRSI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.seti, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 210 CSRRCI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clri, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 211 212 EBREAK -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 213 ECALL -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 214 SRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 215 MRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 216 DRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 217 WFI -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.csr, CSROpType.wfi, SelImm.X , xWen = T, noSpec = T, blockBack = T), 218 219 SFENCE_VMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 220 FENCE_I -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fencei, SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 221 FENCE -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fence , SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 222 223 // A-type 224 AMOADD_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 225 AMOXOR_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 226 AMOSWAP_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 227 AMOAND_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 228 AMOOR_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 229 AMOMIN_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 230 AMOMINU_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 231 AMOMAX_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 232 AMOMAXU_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 233 234 AMOADD_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 235 AMOXOR_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 236 AMOSWAP_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 237 AMOAND_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 238 AMOOR_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 239 AMOMIN_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 240 AMOMINU_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 241 AMOMAX_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 242 AMOMAXU_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 243 244 LR_W -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 245 LR_D -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 246 SC_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 247 SC_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 248 249 ANDN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.andn, SelImm.X, xWen = T), 250 ORN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.orn , SelImm.X, xWen = T), 251 XNOR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xnor, SelImm.X, xWen = T), 252 ORC_B -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.orcb, SelImm.X, xWen = T), 253 254 MIN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.min , SelImm.X, xWen = T), 255 MINU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.minu, SelImm.X, xWen = T), 256 MAX -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.max , SelImm.X, xWen = T), 257 MAXU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.maxu, SelImm.X, xWen = T), 258 259 SEXT_B -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sextb, SelImm.X, xWen = T), 260 PACKH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packh, SelImm.X, xWen = T), 261 SEXT_H -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sexth, SelImm.X, xWen = T), 262 PACKW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packw, SelImm.X, xWen = T), 263 BREV8 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.revb , SelImm.X, xWen = T), 264 REV8 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.rev8 , SelImm.X, xWen = T), 265 PACK -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.pack , SelImm.X, xWen = T), 266 267 BSET -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bset, SelImm.X , xWen = T), 268 BSETI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bset, SelImm.IMM_I, xWen = T), 269 BCLR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bclr, SelImm.X , xWen = T), 270 BCLRI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bclr, SelImm.IMM_I, xWen = T), 271 BINV -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.binv, SelImm.X , xWen = T), 272 BINVI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.binv, SelImm.IMM_I, xWen = T), 273 BEXT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bext, SelImm.X , xWen = T), 274 BEXTI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bext, SelImm.IMM_I, xWen = T), 275 276 ROR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.ror, SelImm.X , xWen = T), 277 RORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.ror, SelImm.IMM_I , xWen = T), 278 ROL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rol, SelImm.X , xWen = T), 279 280 SH1ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1add , SelImm.X , xWen = T), 281 SH2ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2add , SelImm.X , xWen = T), 282 SH3ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3add , SelImm.X , xWen = T), 283 SH1ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1adduw, SelImm.X , xWen = T), 284 SH2ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2adduw, SelImm.X , xWen = T), 285 SH3ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3adduw, SelImm.X , xWen = T), 286 ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.adduw , SelImm.X , xWen = T), 287 SLLI_UW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slliuw , SelImm.IMM_I, xWen = T), 288 ) 289} 290 291/** 292 * FP Decode constants 293 */ 294object FpDecode extends DecodeConstants{ 295 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 296 FLW -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw, selImm = SelImm.IMM_I, fWen = T), 297 FLD -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld, selImm = SelImm.IMM_I, fWen = T), 298 FSW -> FDecode(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sw, selImm = SelImm.IMM_S ), 299 FSD -> FDecode(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sd, selImm = SelImm.IMM_S ), 300 301 FCLASS_S-> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 302 FCLASS_D-> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 303 304 FMV_X_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 305 FMV_X_W -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 306 307 FMV_D_X -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 308 FMV_W_X -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 309 310 FSGNJ_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 311 FSGNJ_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 312 FSGNJX_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 313 FSGNJX_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 314 FSGNJN_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 315 FSGNJN_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 316 317 // FP to FP 318 FCVT_S_D -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 319 FCVT_D_S -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 320 321 // Int to FP 322 FCVT_S_W -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 323 FCVT_S_WU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 324 FCVT_S_L -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 325 FCVT_S_LU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 326 327 FCVT_D_W -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 328 FCVT_D_WU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 329 FCVT_D_L -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 330 FCVT_D_LU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 331 332 // FP to Int 333 FCVT_W_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 334 FCVT_WU_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 335 FCVT_L_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 336 FCVT_LU_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 337 338 FCVT_W_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 339 FCVT_WU_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 340 FCVT_L_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 341 FCVT_LU_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 342 343 FEQ_S -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 344 FLT_S -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 345 FLE_S -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 346 347 FEQ_D -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 348 FLT_D -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 349 FLE_D -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 350 351 FMIN_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 352 FMAX_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 353 FMIN_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 354 FMAX_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 355 356 FADD_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 357 FSUB_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 358 FMUL_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 359 FADD_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 360 FSUB_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 361 FMUL_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 362 363 FMADD_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 364 FMSUB_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 365 FNMADD_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 366 FNMSUB_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 367 FMADD_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 368 FMSUB_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 369 FNMADD_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 370 FNMSUB_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 371 ) 372} 373 374/** 375 * Bit Manipulation Decode 376 */ 377object BDecode extends DecodeConstants{ 378 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 379 // Basic bit manipulation 380 CLZ -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.clz, SelImm.X, xWen = T), 381 CTZ -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.ctz, SelImm.X, xWen = T), 382 CPOP -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpop, SelImm.X, xWen = T), 383 XPERM8 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermb, SelImm.X, xWen = T), 384 XPERM4 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermn, SelImm.X, xWen = T), 385 386 CLZW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.clzw, SelImm.X, xWen = T), 387 CTZW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.ctzw, SelImm.X, xWen = T), 388 CPOPW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpopw, SelImm.X, xWen = T), 389 390 CLMUL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmul, SelImm.X, xWen = T), 391 CLMULH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulh, SelImm.X, xWen = T), 392 CLMULR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulr, SelImm.X, xWen = T), 393 394 AES64ES -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64es, SelImm.X , xWen = T), 395 AES64ESM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64esm, SelImm.X , xWen = T), 396 AES64DS -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ds, SelImm.X , xWen = T), 397 AES64DSM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64dsm, SelImm.X , xWen = T), 398 AES64IM -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.aes64im, SelImm.X , xWen = T), 399 AES64KS1I -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.bku, BKUOpType.aes64ks1i, SelImm.IMM_I, xWen = T), 400 AES64KS2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ks2, SelImm.X , xWen = T), 401 SHA256SUM0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum0, SelImm.X , xWen = T), 402 SHA256SUM1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum1, SelImm.X , xWen = T), 403 SHA256SIG0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig0, SelImm.X , xWen = T), 404 SHA256SIG1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig1, SelImm.X , xWen = T), 405 SHA512SUM0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum0, SelImm.X , xWen = T), 406 SHA512SUM1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum1, SelImm.X , xWen = T), 407 SHA512SIG0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig0, SelImm.X , xWen = T), 408 SHA512SIG1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig1, SelImm.X , xWen = T), 409 SM3P0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p0, SelImm.X , xWen = T), 410 SM3P1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p1, SelImm.X , xWen = T), 411 SM4KS0 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks0, SelImm.X , xWen = T), 412 SM4KS1 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks1, SelImm.X , xWen = T), 413 SM4KS2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks2, SelImm.X , xWen = T), 414 SM4KS3 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks3, SelImm.X , xWen = T), 415 SM4ED0 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed0, SelImm.X , xWen = T), 416 SM4ED1 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed1, SelImm.X , xWen = T), 417 SM4ED2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed2, SelImm.X , xWen = T), 418 SM4ED3 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed3, SelImm.X , xWen = T), 419 ) 420} 421 422/** 423 * FP Divide SquareRoot Constants 424 */ 425object FDivSqrtDecode extends DecodeConstants { 426 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 427 FDIV_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 428 FDIV_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 429 FSQRT_S -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 430 FSQRT_D -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 431 ) 432} 433 434/** 435 * Svinval extension Constants 436 */ 437object SvinvalDecode extends DecodeConstants { 438 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 439 /* sinval_vma is like sfence.vma , but sinval_vma can be dispatched and issued like normal instructions while sfence.vma 440 * must assure it is the ONLY instrucion executing in backend. 441 */ 442 SINVAL_VMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, SelImm.X), 443 /* sfecne.w.inval is the begin instrucion of a TLB flush which set *noSpecExec* and *blockBackward* signals 444 * so when it comes to dispatch , it will block all instruction after itself until all instrucions ahead of it in rob commit 445 * then dispatch and issue this instrucion to flush sbuffer to dcache 446 * after this instrucion commits , issue following sinval_vma instructions (out of order) to flush TLB 447 */ 448 SFENCE_W_INVAL -> XSDecode(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, SelImm.X, noSpec = T, blockBack = T), 449 /* sfecne.inval.ir is the end instrucion of a TLB flush which set *noSpecExec* *blockBackward* and *flushPipe* signals 450 * so when it comes to dispatch , it will wait until all sinval_vma ahead of it in rob commit 451 * then dispatch and issue this instrucion 452 * when it commit at the head of rob , flush the pipeline since some instrucions have been fetched to ibuffer using old TLB map 453 */ 454 SFENCE_INVAL_IR -> XSDecode(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, SelImm.X, noSpec = T, blockBack = T, flushPipe = T) 455 /* what is Svinval extension ? 456 * -----> sfecne.w.inval 457 * sfence.vma vpn1 -----> sinval_vma vpn1 458 * sfence.vma vpn2 -----> sinval_vma vpn2 459 * -----> sfecne.inval.ir 460 * 461 * sfence.vma should be executed in-order and it flushes the pipeline after committing 462 * we can parallel sfence instrucions with this extension 463 */ 464 ) 465} 466 467/* 468 * CBO decode 469 */ 470object CBODecode extends DecodeConstants { 471 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 472 CBO_ZERO -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_zero , SelImm.IMM_S), 473 CBO_CLEAN -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_clean, SelImm.IMM_S), 474 CBO_FLUSH -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_flush, SelImm.IMM_S), 475 CBO_INVAL -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_inval, SelImm.IMM_S) 476 ) 477} 478 479/** 480 * XiangShan Trap Decode constants 481 */ 482object XSTrapDecode extends DecodeConstants { 483 def TRAP = BitPat("b000000000000?????000000001101011") 484 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 485 TRAP -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add, SelImm.IMM_I, xWen = T, xsTrap = T, noSpec = T, blockBack = T) 486 ) 487} 488 489//object Imm32Gen { 490// def apply(sel: UInt, inst: UInt) = { 491// val sign = Mux(sel === SelImm.IMM_Z, 0.S, inst(31).asSInt) 492// val b30_20 = Mux(sel === SelImm.IMM_U, inst(30,20).asSInt, sign) 493// val b19_12 = Mux(sel =/= SelImm.IMM_U && sel =/= SelImm.IMM_UJ, sign, inst(19,12).asSInt) 494// val b11 = Mux(sel === SelImm.IMM_U || sel === SelImm.IMM_Z, 0.S, 495// Mux(sel === SelImm.IMM_UJ, inst(20).asSInt, 496// Mux(sel === SelImm.IMM_SB, inst(7).asSInt, sign))) 497// val b10_5 = Mux(sel === SelImm.IMM_U || sel === SelImm.IMM_Z, 0.U(1.W), inst(30,25)) 498// val b4_1 = Mux(sel === SelImm.IMM_U, 0.U(1.W), 499// Mux(sel === SelImm.IMM_S || sel === SelImm.IMM_SB, inst(11,8), 500// Mux(sel === SelImm.IMM_Z, inst(19,16), inst(24,21)))) 501// val b0 = Mux(sel === SelImm.IMM_S, inst(7), 502// Mux(sel === SelImm.IMM_I, inst(20), 503// Mux(sel === SelImm.IMM_Z, inst(15), 0.U(1.W)))) 504// 505// Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0) 506// } 507//} 508 509abstract class Imm(val len: Int) extends Bundle { 510 def toImm32(minBits: UInt): UInt = do_toImm32(minBits(len - 1, 0)) 511 def do_toImm32(minBits: UInt): UInt 512 def minBitsFromInstr(instr: UInt): UInt 513} 514 515case class Imm_I() extends Imm(12) { 516 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits(len - 1, 0), 32) 517 518 override def minBitsFromInstr(instr: UInt): UInt = 519 Cat(instr(31, 20)) 520} 521 522case class Imm_S() extends Imm(12) { 523 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 524 525 override def minBitsFromInstr(instr: UInt): UInt = 526 Cat(instr(31, 25), instr(11, 7)) 527} 528 529case class Imm_B() extends Imm(12) { 530 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 531 532 override def minBitsFromInstr(instr: UInt): UInt = 533 Cat(instr(31), instr(7), instr(30, 25), instr(11, 8)) 534} 535 536case class Imm_U() extends Imm(20){ 537 override def do_toImm32(minBits: UInt): UInt = Cat(minBits(len - 1, 0), 0.U(12.W)) 538 539 override def minBitsFromInstr(instr: UInt): UInt = { 540 instr(31, 12) 541 } 542} 543 544case class Imm_J() extends Imm(20){ 545 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 546 547 override def minBitsFromInstr(instr: UInt): UInt = { 548 Cat(instr(31), instr(19, 12), instr(20), instr(30, 25), instr(24, 21)) 549 } 550} 551 552case class Imm_Z() extends Imm(12 + 5){ 553 override def do_toImm32(minBits: UInt): UInt = minBits 554 555 override def minBitsFromInstr(instr: UInt): UInt = { 556 Cat(instr(19, 15), instr(31, 20)) 557 } 558} 559 560case class Imm_B6() extends Imm(6){ 561 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 562 563 override def minBitsFromInstr(instr: UInt): UInt = { 564 instr(25, 20) 565 } 566} 567 568case class Imm_OPIVIS() extends Imm(5){ 569 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 570 571 override def minBitsFromInstr(instr: UInt): UInt = { 572 instr(19, 15) 573 } 574} 575case class Imm_OPIVIU() extends Imm(5){ 576 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 577 578 override def minBitsFromInstr(instr: UInt): UInt = { 579 instr(19, 15) 580 } 581} 582case class Imm_VSETVLI() extends Imm(11){ 583 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 584 585 override def minBitsFromInstr(instr: UInt): UInt = { 586 instr(30, 20) 587 } 588} 589case class Imm_VSETIVLI() extends Imm(15){ 590 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 591 592 override def minBitsFromInstr(instr: UInt): UInt = { 593 Cat(instr(19, 15), instr(29, 20)) 594 } 595} 596object ImmUnion { 597 val I = Imm_I() 598 val S = Imm_S() 599 val B = Imm_B() 600 val U = Imm_U() 601 val J = Imm_J() 602 val Z = Imm_Z() 603 val B6 = Imm_B6() 604 val OPIVIS = Imm_OPIVIS() 605 val OPIVIU = Imm_OPIVIU() 606 val VSETVLI = Imm_VSETVLI() 607 val VSETIVLI = Imm_VSETIVLI() 608 609 val imms = Seq(I, S, B, U, J, Z, B6, OPIVIS, OPIVIU, VSETVLI, VSETIVLI) 610 val maxLen = imms.maxBy(_.len).len 611 val immSelMap = Seq( 612 SelImm.IMM_I, 613 SelImm.IMM_S, 614 SelImm.IMM_SB, 615 SelImm.IMM_U, 616 SelImm.IMM_UJ, 617 SelImm.IMM_Z, 618 SelImm.IMM_B6, 619 SelImm.IMM_OPIVIS, 620 SelImm.IMM_OPIVIU, 621 SelImm.IMM_VSETVLI, 622 SelImm.IMM_VSETIVLI 623 ).zip(imms) 624 println(s"ImmUnion max len: $maxLen") 625} 626 627case class Imm_LUI_LOAD() { 628 def immFromLuiLoad(lui_imm: UInt, load_imm: UInt): UInt = { 629 val loadImm = load_imm(Imm_I().len - 1, 0) 630 Cat(lui_imm(Imm_U().len - loadImm.getWidth - 1, 0), loadImm) 631 } 632 def getLuiImm(uop: MicroOp): UInt = { 633 val loadImmLen = Imm_I().len 634 val imm_u = Cat(uop.psrc(1), uop.psrc(0), uop.ctrl.imm(ImmUnion.maxLen - 1, loadImmLen)) 635 Imm_U().do_toImm32(imm_u) 636 } 637} 638 639/** 640 * IO bundle for the Decode unit 641 */ 642class DecodeUnitIO(implicit p: Parameters) extends XSBundle { 643 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 644 val vconfig = Input(UInt(XLEN.W)) 645 val deq = new Bundle { 646 val cf_ctrl = Output(new CfCtrl) 647 val isVset = Output(Bool()) 648 } 649 val deq_isVset = new Bundle{ } 650 val csrCtrl = Input(new CustomCSRCtrlIO) 651} 652 653/** 654 * Decode unit that takes in a single CtrlFlow and generates a CfCtrl. 655 */ 656class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstants { 657 val io = IO(new DecodeUnitIO) 658 659 val ctrl_flow = Wire(new CtrlFlow) // input with RVC Expanded 660 val cf_ctrl = Wire(new CfCtrl) 661 662 ctrl_flow := io.enq.ctrl_flow 663 664 val decode_table: Array[(BitPat, List[BitPat])] = XDecode.table ++ 665 FpDecode.table ++ 666 FDivSqrtDecode.table ++ 667 X64Decode.table ++ 668 XSTrapDecode.table ++ 669 BDecode.table ++ 670 CBODecode.table ++ 671 SvinvalDecode.table ++ 672 VecDecoder.table 673 674 require(decode_table.map(_._2.length == 13).reduce(_ && _), "Decode tables have different column size") 675 // assertion for LUI: only LUI should be assigned `selImm === SelImm.IMM_U && fuType === FuType.alu` 676 val luiMatch = (t: Seq[BitPat]) => t(3).value == FuType.alu.litValue && t.reverse.head.value == SelImm.IMM_U.litValue 677 val luiTable = decode_table.filter(t => luiMatch(t._2)).map(_._1).distinct 678 assert(luiTable.length == 1 && luiTable.head == LUI, "Conflicts: LUI is determined by FuType and SelImm in Dispatch") 679 680 // output 681 cf_ctrl.cf := ctrl_flow 682 val cs: CtrlSignals = Wire(new CtrlSignals()).decode(ctrl_flow.instr, decode_table) 683 cs.singleStep := false.B 684 cs.replayInst := false.B 685 686 val fpDecoder = Module(new FPDecoder) 687 fpDecoder.io.instr := ctrl_flow.instr 688 cs.fpu := fpDecoder.io.fpCtrl 689 690 // TODO: vec decode 691 // FIXME: only 3 src 692 cs.srcType(3) := DontCare 693 cs.lsrc(3) := DontCare 694 cs.uopIdx := "b11111".U 695 696 val isMove = BitPat("b000000000000_?????_000_?????_0010011") === ctrl_flow.instr 697 cs.isMove := isMove && ctrl_flow.instr(RD_MSB, RD_LSB) =/= 0.U 698 699 // read src1~3 location 700 cs.lsrc(0) := ctrl_flow.instr(RS1_MSB, RS1_LSB) 701 cs.lsrc(1) := ctrl_flow.instr(RS2_MSB, RS2_LSB) 702 cs.lsrc(2) := ctrl_flow.instr(RS3_MSB, RS3_LSB) 703 // read dest location 704 cs.ldest := ctrl_flow.instr(RD_MSB, RD_LSB) 705 706 // fill in exception vector 707 cf_ctrl.cf.exceptionVec := io.enq.ctrl_flow.exceptionVec 708 cf_ctrl.cf.exceptionVec(illegalInstr) := cs.selImm === SelImm.INVALID_INSTR 709 710 when (!io.csrCtrl.svinval_enable) { 711 val base_ii = cs.selImm === SelImm.INVALID_INSTR 712 val sinval = BitPat("b0001011_?????_?????_000_00000_1110011") === ctrl_flow.instr 713 val w_inval = BitPat("b0001100_00000_00000_000_00000_1110011") === ctrl_flow.instr 714 val inval_ir = BitPat("b0001100_00001_00000_000_00000_1110011") === ctrl_flow.instr 715 val svinval_ii = sinval || w_inval || inval_ir 716 cf_ctrl.cf.exceptionVec(illegalInstr) := base_ii || svinval_ii 717 cs.flushPipe := false.B 718 } 719 720 // fix frflags 721 // fflags zero csrrs rd csr 722 val isFrflags = BitPat("b000000000001_00000_010_?????_1110011") === ctrl_flow.instr 723 when (cs.fuType === FuType.csr && isFrflags) { 724 cs.blockBackward := false.B 725 } 726 727 cs.imm := LookupTree(cs.selImm, ImmUnion.immSelMap.map( 728 x => { 729 val minBits = x._2.minBitsFromInstr(ctrl_flow.instr) 730 require(minBits.getWidth == x._2.len) 731 x._1 -> minBits 732 } 733 )) 734 735 cs.vconfig := 0.U(16.W) 736 when(FuType.isVpu(cs.fuType)){ 737 cs.vconfig := io.vconfig 738 } 739 cf_ctrl.ctrl := cs 740 741 io.deq.cf_ctrl := cf_ctrl 742 743 io.deq.isVset := FuType.isIntExu(cs.fuType) && ALUOpType.isVset(cs.fuOpType) 744 745 //------------------------------------------------------------- 746 // Debug Info 747 XSDebug("in: instr=%x pc=%x excepVec=%b crossPageIPFFix=%d\n", 748 io.enq.ctrl_flow.instr, io.enq.ctrl_flow.pc, io.enq.ctrl_flow.exceptionVec.asUInt, 749 io.enq.ctrl_flow.crossPageIPFFix) 750 XSDebug("out: srcType(0)=%b srcType(1)=%b srcType(2)=%b lsrc(0)=%d lsrc(1)=%d lsrc(2)=%d ldest=%d fuType=%b fuOpType=%b\n", 751 io.deq.cf_ctrl.ctrl.srcType(0), io.deq.cf_ctrl.ctrl.srcType(1), io.deq.cf_ctrl.ctrl.srcType(2), 752 io.deq.cf_ctrl.ctrl.lsrc(0), io.deq.cf_ctrl.ctrl.lsrc(1), io.deq.cf_ctrl.ctrl.lsrc(2), 753 io.deq.cf_ctrl.ctrl.ldest, io.deq.cf_ctrl.ctrl.fuType, io.deq.cf_ctrl.ctrl.fuOpType) 754 XSDebug("out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d flushPipe=%d imm=%x\n", 755 io.deq.cf_ctrl.ctrl.rfWen, io.deq.cf_ctrl.ctrl.fpWen, io.deq.cf_ctrl.ctrl.isXSTrap, 756 io.deq.cf_ctrl.ctrl.noSpecExec, io.deq.cf_ctrl.ctrl.blockBackward, io.deq.cf_ctrl.ctrl.flushPipe, 757 io.deq.cf_ctrl.ctrl.imm) 758 XSDebug("out: excepVec=%b\n", io.deq.cf_ctrl.cf.exceptionVec.asUInt) 759} 760