1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions._ 23import freechips.rocketchip.util.uintToBitPat 24import utility._ 25import utils._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.FuType 29import xiangshan.backend.Bundles.{DecodedInst, DynInst, StaticInst} 30import xiangshan.backend.decode.isa.bitfield.{InstVType, XSInstBitFields} 31import xiangshan.backend.fu.vector.Bundles.VType 32 33/** 34 * Abstract trait giving defaults and other relevant values to different Decode constants/ 35 */ 36abstract trait DecodeConstants { 37 // This X should be used only in 1-bit signal. Otherwise, use BitPat("b???") to align with the width of UInt. 38 def X = BitPat("b0") 39 def N = BitPat("b0") 40 def Y = BitPat("b1") 41 def T = true 42 def F = false 43 44 def decodeDefault: List[BitPat] = // illegal instruction 45 // srcType(0) srcType(1) srcType(2) fuType fuOpType rfWen 46 // | | | | | | fpWen 47 // | | | | | | | vecWen 48 // | | | | | | | | isXSTrap 49 // | | | | | | | | | noSpecExec 50 // | | | | | | | | | | blockBackward 51 // | | | | | | | | | | | flushPipe 52 // | | | | | | | | | | | | canRobCompress 53 // | | | | | | | | | | | | | uopSplitType 54 // | | | | | | | | | | | | | | selImm 55 List(SrcType.X, SrcType.X, SrcType.X, FuType.X, FuOpType.X, N, N, N, N, N, N, N, N, UopSplitType.X, SelImm.INVALID_INSTR) // Use SelImm to indicate invalid instr 56 57 val decodeArray: Array[(BitPat, XSDecodeBase)] 58 final def table: Array[(BitPat, List[BitPat])] = decodeArray.map(x => (x._1, x._2.generate())) 59} 60 61trait DecodeUnitConstants 62{ 63 // abstract out instruction decode magic numbers 64 val RD_MSB = 11 65 val RD_LSB = 7 66 val RS1_MSB = 19 67 val RS1_LSB = 15 68 val RS2_MSB = 24 69 val RS2_LSB = 20 70 val RS3_MSB = 31 71 val RS3_LSB = 27 72} 73 74/** 75 * Decoded control signals 76 * See xiangshan/package.scala, xiangshan/backend/package.scala, Bundle.scala 77 */ 78 79abstract class XSDecodeBase { 80 def X = BitPat("b?") 81 def N = BitPat("b0") 82 def Y = BitPat("b1") 83 def T = true 84 def F = false 85 def generate() : List[BitPat] 86} 87 88case class XSDecode( 89 src1: BitPat, src2: BitPat, src3: BitPat, 90 fu: FuType.OHType, fuOp: BitPat, selImm: BitPat, 91 uopSplitType: BitPat = UopSplitType.X, 92 xWen: Boolean = false, 93 fWen: Boolean = false, 94 vWen: Boolean = false, 95 mWen: Boolean = false, 96 xsTrap: Boolean = false, 97 noSpec: Boolean = false, 98 blockBack: Boolean = false, 99 flushPipe: Boolean = false, 100 canRobCompress: Boolean = false, 101) extends XSDecodeBase { 102 def generate() : List[BitPat] = { 103 List (src1, src2, src3, BitPat(fu.U(FuType.num.W)), fuOp, xWen.B, fWen.B, (vWen || mWen).B, xsTrap.B, noSpec.B, blockBack.B, flushPipe.B, canRobCompress.B, uopSplitType, selImm) 104 } 105} 106 107case class FDecode( 108 src1: BitPat, src2: BitPat, src3: BitPat, 109 fu: FuType.OHType, fuOp: BitPat, selImm: BitPat = SelImm.X, 110 uopSplitType: BitPat = UopSplitType.X, 111 xWen: Boolean = false, 112 fWen: Boolean = false, 113 vWen: Boolean = false, 114 mWen: Boolean = false, 115 xsTrap: Boolean = false, 116 noSpec: Boolean = false, 117 blockBack: Boolean = false, 118 flushPipe: Boolean = false, 119 canRobCompress: Boolean = false, 120) extends XSDecodeBase { 121 def generate() : List[BitPat] = { 122 XSDecode(src1, src2, src3, fu, fuOp, selImm, uopSplitType, xWen, fWen, vWen, mWen, xsTrap, noSpec, blockBack, flushPipe, canRobCompress).generate() 123 } 124} 125 126/** 127 * Decode constants for RV64 128 */ 129object X64Decode extends DecodeConstants { 130 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 131 LD -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld , SelImm.IMM_I, xWen = T), 132 LWU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lwu , SelImm.IMM_I, xWen = T), 133 SD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sd , SelImm.IMM_S ), 134 135 SLLI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sll , SelImm.IMM_I, xWen = T, canRobCompress = T), 136 SRLI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srl , SelImm.IMM_I, xWen = T, canRobCompress = T), 137 SRAI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sra , SelImm.IMM_I, xWen = T, canRobCompress = T), 138 139 ADDIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.addw, SelImm.IMM_I, xWen = T, canRobCompress = T), 140 SLLIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sllw, SelImm.IMM_I, xWen = T, canRobCompress = T), 141 SRAIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sraw, SelImm.IMM_I, xWen = T, canRobCompress = T), 142 SRLIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srlw, SelImm.IMM_I, xWen = T, canRobCompress = T), 143 144 ADDW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.addw, SelImm.X , xWen = T, canRobCompress = T), 145 SUBW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.subw, SelImm.X , xWen = T, canRobCompress = T), 146 SLLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sllw, SelImm.X , xWen = T, canRobCompress = T), 147 SRAW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sraw, SelImm.X , xWen = T, canRobCompress = T), 148 SRLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srlw, SelImm.X , xWen = T, canRobCompress = T), 149 150 RORW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rorw, SelImm.X , xWen = T, canRobCompress = T), 151 RORIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.rorw, SelImm.IMM_I, xWen = T, canRobCompress = T), 152 ROLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rolw, SelImm.X , xWen = T, canRobCompress = T), 153 ) 154} 155 156/** 157 * Overall Decode constants 158 */ 159object XDecode extends DecodeConstants { 160 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 161 LW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw , SelImm.IMM_I, xWen = T), 162 LH -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lh , SelImm.IMM_I, xWen = T), 163 LHU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lhu , SelImm.IMM_I, xWen = T), 164 LB -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lb , SelImm.IMM_I, xWen = T), 165 LBU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lbu , SelImm.IMM_I, xWen = T), 166 SW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sw , SelImm.IMM_S ), 167 SH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sh , SelImm.IMM_S ), 168 SB -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sb , SelImm.IMM_S ), 169 LUI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add , SelImm.IMM_U, xWen = T, canRobCompress = T), 170 ADDI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add , SelImm.IMM_I, xWen = T, canRobCompress = T), 171 ANDI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.and , SelImm.IMM_I, xWen = T, canRobCompress = T), 172 ORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.or , SelImm.IMM_I, xWen = T, canRobCompress = T), 173 XORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.xor , SelImm.IMM_I, xWen = T, canRobCompress = T), 174 SLTI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slt , SelImm.IMM_I, xWen = T, canRobCompress = T), 175 SLTIU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sltu, SelImm.IMM_I, xWen = T, canRobCompress = T), 176 SLL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sll , SelImm.X , xWen = T, canRobCompress = T), 177 ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.add , SelImm.X , xWen = T, canRobCompress = T), 178 SUB -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sub , SelImm.X , xWen = T, canRobCompress = T), 179 SLT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.slt , SelImm.X , xWen = T, canRobCompress = T), 180 SLTU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sltu, SelImm.X , xWen = T, canRobCompress = T), 181 AND -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.and , SelImm.X , xWen = T, canRobCompress = T), 182 OR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.or , SelImm.X , xWen = T, canRobCompress = T), 183 XOR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xor , SelImm.X , xWen = T, canRobCompress = T), 184 SRA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sra , SelImm.X , xWen = T, canRobCompress = T), 185 SRL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srl , SelImm.X , xWen = T, canRobCompress = T), 186 187 MUL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mul , SelImm.X, xWen = T, canRobCompress = T), 188 MULH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulh , SelImm.X, xWen = T, canRobCompress = T), 189 MULHU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhu , SelImm.X, xWen = T, canRobCompress = T), 190 MULHSU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhsu, SelImm.X, xWen = T, canRobCompress = T), 191 MULW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulw , SelImm.X, xWen = T, canRobCompress = T), 192 193 DIV -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.div , SelImm.X, xWen = T, canRobCompress = T), 194 DIVU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divu , SelImm.X, xWen = T, canRobCompress = T), 195 REM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.rem , SelImm.X, xWen = T, canRobCompress = T), 196 REMU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remu , SelImm.X, xWen = T, canRobCompress = T), 197 DIVW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divw , SelImm.X, xWen = T, canRobCompress = T), 198 DIVUW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divuw , SelImm.X, xWen = T, canRobCompress = T), 199 REMW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remw , SelImm.X, xWen = T, canRobCompress = T), 200 REMUW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remuw , SelImm.X, xWen = T, canRobCompress = T), 201 202 AUIPC -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.auipc, SelImm.IMM_U , xWen = T), 203 JAL -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jal , SelImm.IMM_UJ, xWen = T), 204 JALR -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jalr , SelImm.IMM_I , uopSplitType = UopSplitType.SCA_SIM, xWen = T), 205 BEQ -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.beq , SelImm.IMM_SB ), 206 BNE -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bne , SelImm.IMM_SB ), 207 BGE -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bge , SelImm.IMM_SB ), 208 BGEU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bgeu , SelImm.IMM_SB ), 209 BLT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.blt , SelImm.IMM_SB ), 210 BLTU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bltu , SelImm.IMM_SB ), 211 212 // I-type, the immediate12 holds the CSR register. 213 CSRRW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrt , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 214 CSRRS -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.set , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 215 CSRRC -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clr , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 216 217 CSRRWI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrti, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 218 CSRRSI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.seti, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 219 CSRRCI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clri, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 220 221 EBREAK -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 222 ECALL -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 223 SRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 224 MRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 225 DRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 226 WFI -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.csr, CSROpType.wfi, SelImm.X , xWen = T, noSpec = T, blockBack = T), 227 228 SFENCE_VMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 229 FENCE_I -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fencei, SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 230 FENCE -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fence , SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 231 232 // A-type 233 AMOADD_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 234 AMOXOR_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 235 AMOSWAP_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 236 AMOAND_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 237 AMOOR_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 238 AMOMIN_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 239 AMOMINU_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 240 AMOMAX_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 241 AMOMAXU_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 242 243 AMOADD_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 244 AMOXOR_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 245 AMOSWAP_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 246 AMOAND_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 247 AMOOR_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 248 AMOMIN_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 249 AMOMINU_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 250 AMOMAX_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 251 AMOMAXU_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 252 253 LR_W -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 254 LR_D -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 255 SC_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 256 SC_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 257 258 ANDN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.andn, SelImm.X, xWen = T, canRobCompress = T), 259 ORN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.orn , SelImm.X, xWen = T, canRobCompress = T), 260 XNOR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xnor, SelImm.X, xWen = T, canRobCompress = T), 261 ORC_B -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.orcb, SelImm.X, xWen = T, canRobCompress = T), 262 263 MIN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.min , SelImm.X, xWen = T, canRobCompress = T), 264 MINU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.minu, SelImm.X, xWen = T, canRobCompress = T), 265 MAX -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.max , SelImm.X, xWen = T, canRobCompress = T), 266 MAXU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.maxu, SelImm.X, xWen = T, canRobCompress = T), 267 268 SEXT_B -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sextb, SelImm.X, xWen = T, canRobCompress = T), 269 PACKH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packh, SelImm.X, xWen = T, canRobCompress = T), 270 SEXT_H -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sexth, SelImm.X, xWen = T, canRobCompress = T), 271 PACKW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packw, SelImm.X, xWen = T, canRobCompress = T), 272 BREV8 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.revb , SelImm.X, xWen = T, canRobCompress = T), 273 REV8 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.rev8 , SelImm.X, xWen = T, canRobCompress = T), 274 PACK -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.pack , SelImm.X, xWen = T, canRobCompress = T), 275 276 BSET -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bset, SelImm.X , xWen = T, canRobCompress = T), 277 BSETI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bset, SelImm.IMM_I, xWen = T, canRobCompress = T), 278 BCLR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bclr, SelImm.X , xWen = T, canRobCompress = T), 279 BCLRI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bclr, SelImm.IMM_I, xWen = T, canRobCompress = T), 280 BINV -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.binv, SelImm.X , xWen = T, canRobCompress = T), 281 BINVI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.binv, SelImm.IMM_I, xWen = T, canRobCompress = T), 282 BEXT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bext, SelImm.X , xWen = T, canRobCompress = T), 283 BEXTI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bext, SelImm.IMM_I, xWen = T, canRobCompress = T), 284 285 ROR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.ror, SelImm.X , xWen = T, canRobCompress = T), 286 RORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.ror, SelImm.IMM_I , xWen = T, canRobCompress = T), 287 ROL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rol, SelImm.X , xWen = T, canRobCompress = T), 288 289 SH1ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1add , SelImm.X , xWen = T, canRobCompress = T), 290 SH2ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2add , SelImm.X , xWen = T, canRobCompress = T), 291 SH3ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3add , SelImm.X , xWen = T, canRobCompress = T), 292 SH1ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1adduw, SelImm.X , xWen = T, canRobCompress = T), 293 SH2ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2adduw, SelImm.X , xWen = T, canRobCompress = T), 294 SH3ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3adduw, SelImm.X , xWen = T, canRobCompress = T), 295 ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.adduw , SelImm.X , xWen = T, canRobCompress = T), 296 SLLI_UW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slliuw , SelImm.IMM_I, xWen = T, canRobCompress = T), 297 ) 298} 299 300/** 301 * FP Decode constants 302 */ 303object FpDecode extends DecodeConstants{ 304 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 305 FLW -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw, selImm = SelImm.IMM_I, fWen = T), 306 FLD -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld, selImm = SelImm.IMM_I, fWen = T), 307 FSW -> FDecode(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sw, selImm = SelImm.IMM_S ), 308 FSD -> FDecode(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sd, selImm = SelImm.IMM_S ), 309 310 FMV_D_X -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2v, IF2VectorType.FMX_D_X, fWen = T, canRobCompress = T), 311 FMV_W_X -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2v, IF2VectorType.FMX_W_X, fWen = T, canRobCompress = T), 312 313 // Int to FP 314 FCVT_S_W -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 315 FCVT_S_WU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 316 FCVT_S_L -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 317 FCVT_S_LU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 318 319 FCVT_D_W -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 320 FCVT_D_WU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 321 FCVT_D_L -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 322 FCVT_D_LU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 323 324 ) 325} 326 327/** 328 * Bit Manipulation Decode 329 */ 330object BDecode extends DecodeConstants{ 331 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 332 // Basic bit manipulation 333 CLZ -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.clz, SelImm.X, xWen = T, canRobCompress = T), 334 CTZ -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.ctz, SelImm.X, xWen = T, canRobCompress = T), 335 CPOP -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpop, SelImm.X, xWen = T, canRobCompress = T), 336 XPERM8 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermb, SelImm.X, xWen = T, canRobCompress = T), 337 XPERM4 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermn, SelImm.X, xWen = T, canRobCompress = T), 338 339 CLZW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.clzw, SelImm.X, xWen = T, canRobCompress = T), 340 CTZW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.ctzw, SelImm.X, xWen = T, canRobCompress = T), 341 CPOPW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpopw, SelImm.X, xWen = T, canRobCompress = T), 342 343 CLMUL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmul, SelImm.X, xWen = T, canRobCompress = T), 344 CLMULH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulh, SelImm.X, xWen = T, canRobCompress = T), 345 CLMULR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulr, SelImm.X, xWen = T, canRobCompress = T), 346 347 AES64ES -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64es, SelImm.X , xWen = T, canRobCompress = T), 348 AES64ESM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64esm, SelImm.X , xWen = T, canRobCompress = T), 349 AES64DS -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ds, SelImm.X , xWen = T, canRobCompress = T), 350 AES64DSM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64dsm, SelImm.X , xWen = T, canRobCompress = T), 351 AES64IM -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.aes64im, SelImm.X , xWen = T, canRobCompress = T), 352 AES64KS1I -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.bku, BKUOpType.aes64ks1i, SelImm.IMM_I, xWen = T, canRobCompress = T), 353 AES64KS2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ks2, SelImm.X , xWen = T, canRobCompress = T), 354 SHA256SUM0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum0, SelImm.X , xWen = T, canRobCompress = T), 355 SHA256SUM1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum1, SelImm.X , xWen = T, canRobCompress = T), 356 SHA256SIG0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig0, SelImm.X , xWen = T, canRobCompress = T), 357 SHA256SIG1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig1, SelImm.X , xWen = T, canRobCompress = T), 358 SHA512SUM0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum0, SelImm.X , xWen = T, canRobCompress = T), 359 SHA512SUM1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum1, SelImm.X , xWen = T, canRobCompress = T), 360 SHA512SIG0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig0, SelImm.X , xWen = T, canRobCompress = T), 361 SHA512SIG1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig1, SelImm.X , xWen = T, canRobCompress = T), 362 SM3P0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p0, SelImm.X , xWen = T, canRobCompress = T), 363 SM3P1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p1, SelImm.X , xWen = T, canRobCompress = T), 364 SM4KS0 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks0, SelImm.X , xWen = T, canRobCompress = T), 365 SM4KS1 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks1, SelImm.X , xWen = T, canRobCompress = T), 366 SM4KS2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks2, SelImm.X , xWen = T, canRobCompress = T), 367 SM4KS3 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks3, SelImm.X , xWen = T, canRobCompress = T), 368 SM4ED0 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed0, SelImm.X , xWen = T, canRobCompress = T), 369 SM4ED1 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed1, SelImm.X , xWen = T, canRobCompress = T), 370 SM4ED2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed2, SelImm.X , xWen = T, canRobCompress = T), 371 SM4ED3 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed3, SelImm.X , xWen = T, canRobCompress = T), 372 ) 373} 374 375/** 376 * FP Divide SquareRoot Constants 377 */ 378object FDivSqrtDecode extends DecodeConstants { 379 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 380 FDIV_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T, canRobCompress = T), 381 FDIV_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T, canRobCompress = T), 382 FSQRT_S -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T, canRobCompress = T), 383 FSQRT_D -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T, canRobCompress = T), 384 ) 385} 386 387/** 388 * Svinval extension Constants 389 */ 390object SvinvalDecode extends DecodeConstants { 391 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 392 /* sinval_vma is like sfence.vma , but sinval_vma can be dispatched and issued like normal instructions while sfence.vma 393 * must assure it is the ONLY instrucion executing in backend. 394 */ 395 SINVAL_VMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, SelImm.X), 396 /* sfecne.w.inval is the begin instrucion of a TLB flush which set *noSpecExec* and *blockBackward* signals 397 * so when it comes to dispatch , it will block all instruction after itself until all instrucions ahead of it in rob commit 398 * then dispatch and issue this instrucion to flush sbuffer to dcache 399 * after this instrucion commits , issue following sinval_vma instructions (out of order) to flush TLB 400 */ 401 SFENCE_W_INVAL -> XSDecode(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, SelImm.X, noSpec = T, blockBack = T), 402 /* sfecne.inval.ir is the end instrucion of a TLB flush which set *noSpecExec* *blockBackward* and *flushPipe* signals 403 * so when it comes to dispatch , it will wait until all sinval_vma ahead of it in rob commit 404 * then dispatch and issue this instrucion 405 * when it commit at the head of rob , flush the pipeline since some instrucions have been fetched to ibuffer using old TLB map 406 */ 407 SFENCE_INVAL_IR -> XSDecode(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, SelImm.X, noSpec = T, blockBack = T, flushPipe = T) 408 /* what is Svinval extension ? 409 * -----> sfecne.w.inval 410 * sfence.vma vpn1 -----> sinval_vma vpn1 411 * sfence.vma vpn2 -----> sinval_vma vpn2 412 * -----> sfecne.inval.ir 413 * 414 * sfence.vma should be executed in-order and it flushes the pipeline after committing 415 * we can parallel sfence instrucions with this extension 416 */ 417 ) 418} 419 420/* 421 * CBO decode 422 */ 423object CBODecode extends DecodeConstants { 424 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 425 CBO_ZERO -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_zero , SelImm.IMM_S), 426 CBO_CLEAN -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_clean, SelImm.IMM_S), 427 CBO_FLUSH -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_flush, SelImm.IMM_S), 428 CBO_INVAL -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_inval, SelImm.IMM_S) 429 ) 430} 431 432/** 433 * XiangShan Trap Decode constants 434 */ 435object XSTrapDecode extends DecodeConstants { 436 def TRAP = BitPat("b000000000000?????000000001101011") 437 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 438 TRAP -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add, SelImm.IMM_I, xWen = T, xsTrap = T, noSpec = T, blockBack = T) 439 ) 440} 441 442abstract class Imm(val len: Int) extends Bundle { 443 def toImm32(minBits: UInt): UInt = do_toImm32(minBits(len - 1, 0)) 444 def do_toImm32(minBits: UInt): UInt 445 def minBitsFromInstr(instr: UInt): UInt 446} 447 448case class Imm_I() extends Imm(12) { 449 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits(len - 1, 0), 32) 450 451 override def minBitsFromInstr(instr: UInt): UInt = 452 Cat(instr(31, 20)) 453} 454 455case class Imm_S() extends Imm(12) { 456 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 457 458 override def minBitsFromInstr(instr: UInt): UInt = 459 Cat(instr(31, 25), instr(11, 7)) 460} 461 462case class Imm_B() extends Imm(12) { 463 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 464 465 override def minBitsFromInstr(instr: UInt): UInt = 466 Cat(instr(31), instr(7), instr(30, 25), instr(11, 8)) 467} 468 469case class Imm_U() extends Imm(20){ 470 override def do_toImm32(minBits: UInt): UInt = Cat(minBits(len - 1, 0), 0.U(12.W)) 471 472 override def minBitsFromInstr(instr: UInt): UInt = { 473 instr(31, 12) 474 } 475} 476 477case class Imm_J() extends Imm(20){ 478 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 479 480 override def minBitsFromInstr(instr: UInt): UInt = { 481 Cat(instr(31), instr(19, 12), instr(20), instr(30, 25), instr(24, 21)) 482 } 483} 484 485case class Imm_Z() extends Imm(12 + 5){ 486 override def do_toImm32(minBits: UInt): UInt = minBits 487 488 override def minBitsFromInstr(instr: UInt): UInt = { 489 Cat(instr(19, 15), instr(31, 20)) 490 } 491} 492 493case class Imm_B6() extends Imm(6){ 494 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 495 496 override def minBitsFromInstr(instr: UInt): UInt = { 497 instr(25, 20) 498 } 499} 500 501case class Imm_OPIVIS() extends Imm(5){ 502 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 503 504 override def minBitsFromInstr(instr: UInt): UInt = { 505 instr(19, 15) 506 } 507} 508 509case class Imm_OPIVIU() extends Imm(5){ 510 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 511 512 override def minBitsFromInstr(instr: UInt): UInt = { 513 instr(19, 15) 514 } 515} 516 517case class Imm_VSETVLI() extends Imm(11){ 518 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 519 520 override def minBitsFromInstr(instr: UInt): UInt = { 521 instr(30, 20) 522 } 523} 524 525case class Imm_VSETIVLI() extends Imm(13){ 526 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 527 528 override def minBitsFromInstr(instr: UInt): UInt = { 529 val rvInst: XSInstBitFields = instr.asTypeOf(new XSInstBitFields) 530 val uimm5 = rvInst.UIMM_VSETIVLI 531 val vtype8 = rvInst.ZIMM_VTYPE 532 Cat(uimm5, vtype8) 533 } 534 /** 535 * get VType from extended imm 536 * @param extedImm 537 * @return VType 538 */ 539 def getVType(extedImm: UInt): InstVType = { 540 val vtype = Wire(new InstVType) 541 vtype := extedImm(7, 0).asTypeOf(new InstVType) 542 vtype 543 } 544 545 def getAvl(extedImm: UInt): UInt = { 546 extedImm(12, 8) 547 } 548} 549 550case class Imm_LUI32() extends Imm(32){ 551 override def do_toImm32(minBits: UInt): UInt = minBits(31, 0) 552 553 override def minBitsFromInstr(instr: UInt): UInt = { 554 instr(31, 0) 555 } 556} 557 558case class Imm_VRORVI() extends Imm(6){ 559 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 560 561 override def minBitsFromInstr(instr: UInt): UInt = { 562 Cat(instr(26), instr(19, 15)) 563 } 564} 565 566object ImmUnion { 567 val I = Imm_I() 568 val S = Imm_S() 569 val B = Imm_B() 570 val U = Imm_U() 571 val J = Imm_J() 572 val Z = Imm_Z() 573 val B6 = Imm_B6() 574 val OPIVIS = Imm_OPIVIS() 575 val OPIVIU = Imm_OPIVIU() 576 val VSETVLI = Imm_VSETVLI() 577 val VSETIVLI = Imm_VSETIVLI() 578 val LUI32 = Imm_LUI32() 579 val VRORVI = Imm_VRORVI() 580 581 // do not add special type lui32 to this, keep ImmUnion max len being 20. 582 val imms = Seq(I, S, B, U, J, Z, B6, OPIVIS, OPIVIU, VSETVLI, VSETIVLI, VRORVI) 583 val maxLen = imms.maxBy(_.len).len 584 val immSelMap = Seq( 585 SelImm.IMM_I, 586 SelImm.IMM_S, 587 SelImm.IMM_SB, 588 SelImm.IMM_U, 589 SelImm.IMM_UJ, 590 SelImm.IMM_Z, 591 SelImm.IMM_B6, 592 SelImm.IMM_OPIVIS, 593 SelImm.IMM_OPIVIU, 594 SelImm.IMM_VSETVLI, 595 SelImm.IMM_VSETIVLI, 596 SelImm.IMM_VRORVI, 597 ).zip(imms) 598 println(s"ImmUnion max len: $maxLen") 599} 600 601case class Imm_LUI_LOAD() { 602 def immFromLuiLoad(lui_imm: UInt, load_imm: UInt): UInt = { 603 val loadImm = load_imm(Imm_I().len - 1, 0) 604 Cat(lui_imm(ImmUnion.maxLen - loadImm.getWidth - 1, 0), loadImm) 605 } 606 def getLuiImm(uop: DynInst): UInt = { 607 val loadImmLen = Imm_I().len 608 val imm_u = Cat(uop.psrc(1), uop.psrc(0), uop.imm(ImmUnion.maxLen - 1, loadImmLen)) 609 Cat(Imm_U().toImm32(imm_u)(31, loadImmLen), uop.imm(loadImmLen - 1, 0)) 610 } 611} 612 613/** 614 * IO bundle for the Decode unit 615 */ 616class DecodeUnitDeqIO(implicit p: Parameters) extends XSBundle { 617 val decodedInst = Output(new DecodedInst) 618 val isComplex = Output(Bool()) 619 val uopInfo = Output(new UopInfo) 620} 621class DecodeUnitIO(implicit p: Parameters) extends XSBundle { 622 val enq = new Bundle { 623 val ctrlFlow = Input(new StaticInst) 624 val vtype = Input(new VType) 625 } 626// val vconfig = Input(UInt(XLEN.W)) 627 val deq = new DecodeUnitDeqIO 628 val csrCtrl = Input(new CustomCSRCtrlIO) 629} 630 631/** 632 * Decode unit that takes in a single CtrlFlow and generates a CfCtrl. 633 */ 634class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstants { 635 val io = IO(new DecodeUnitIO) 636 637 val ctrl_flow = io.enq.ctrlFlow // input with RVC Expanded 638 639 private val inst: XSInstBitFields = io.enq.ctrlFlow.instr.asTypeOf(new XSInstBitFields) 640 641 val decode_table: Array[(BitPat, List[BitPat])] = XDecode.table ++ 642 FpDecode.table ++ 643// FDivSqrtDecode.table ++ 644 X64Decode.table ++ 645 XSTrapDecode.table ++ 646 BDecode.table ++ 647 CBODecode.table ++ 648 SvinvalDecode.table ++ 649 VecDecoder.table 650 651 require(decode_table.map(_._2.length == 15).reduce(_ && _), "Decode tables have different column size") 652 // assertion for LUI: only LUI should be assigned `selImm === SelImm.IMM_U && fuType === FuType.alu` 653 val luiMatch = (t: Seq[BitPat]) => t(3).value == FuType.alu.ohid && t.reverse.head.value == SelImm.IMM_U.litValue 654 val luiTable = decode_table.filter(t => luiMatch(t._2)).map(_._1).distinct 655 assert(luiTable.length == 1 && luiTable.head == LUI, "Conflicts: LUI is determined by FuType and SelImm in Dispatch") 656 657 // output 658 val decodedInst: DecodedInst = Wire(new DecodedInst()).decode(ctrl_flow.instr, decode_table) 659 660 val fpDecoder = Module(new FPDecoder) 661 fpDecoder.io.instr := ctrl_flow.instr 662 decodedInst.fpu := fpDecoder.io.fpCtrl 663 664 decodedInst.connectStaticInst(io.enq.ctrlFlow) 665 666 decodedInst.uopIdx := 0.U 667 decodedInst.firstUop := true.B 668 decodedInst.lastUop := true.B 669 decodedInst.numUops := 1.U 670 decodedInst.numWB := 1.U 671 672 val isMove = BitPat("b000000000000_?????_000_?????_0010011") === ctrl_flow.instr 673 decodedInst.isMove := isMove && ctrl_flow.instr(RD_MSB, RD_LSB) =/= 0.U && !io.csrCtrl.singlestep 674 675 // fmadd - b1000011 676 // fmsub - b1000111 677 // fnmsub- b1001011 678 // fnmadd- b1001111 679 private val isFMA = inst.OPCODE === BitPat("b100??11") 680 private val isVppu = FuType.isVppu(decodedInst.fuType) 681 private val isVecOPF = FuType.isVecOPF(decodedInst.fuType) 682 683 private val v0Idx = 0 684 private val vconfigIdx = VCONFIG_IDX 685 686 // read src1~3 location 687 decodedInst.lsrc(0) := inst.RS1 688 decodedInst.lsrc(1) := inst.RS2 689 // src(2) of fma is fs3, src(2) of vector inst is old vd 690 decodedInst.lsrc(2) := Mux(isFMA, inst.FS3, inst.VD) 691 decodedInst.lsrc(3) := v0Idx.U 692 decodedInst.lsrc(4) := vconfigIdx.U 693 decodedInst.srcType(3) := Mux(inst.VM.asBool, SrcType.DC, SrcType.vp) // mask src 694 decodedInst.srcType(4) := SrcType.vp // vconfig 695 696 // read dest location 697 decodedInst.ldest := inst.RD 698 699 // fill in exception vector 700 val vecException = Module(new VecExceptionGen) 701 vecException.io.inst := io.enq.ctrlFlow.instr 702 vecException.io.decodedInst := decodedInst 703 vecException.io.vtype := decodedInst.vpu.vtype 704 decodedInst.exceptionVec(illegalInstr) := decodedInst.selImm === SelImm.INVALID_INSTR || vecException.io.illegalInst 705 706 when (!io.csrCtrl.svinval_enable) { 707 val base_ii = decodedInst.selImm === SelImm.INVALID_INSTR || vecException.io.illegalInst 708 val sinval = BitPat("b0001011_?????_?????_000_00000_1110011") === ctrl_flow.instr 709 val w_inval = BitPat("b0001100_00000_00000_000_00000_1110011") === ctrl_flow.instr 710 val inval_ir = BitPat("b0001100_00001_00000_000_00000_1110011") === ctrl_flow.instr 711 val svinval_ii = sinval || w_inval || inval_ir 712 decodedInst.exceptionVec(illegalInstr) := base_ii || svinval_ii 713 decodedInst.flushPipe := false.B 714 } 715 716 // fix frflags 717 // fflags zero csrrs rd csr 718 val isFrflags = BitPat("b000000000001_00000_010_?????_1110011") === ctrl_flow.instr 719 when (decodedInst.fuType === FuType.csr.U && isFrflags) { 720 decodedInst.blockBackward := false.B 721 } 722 723 decodedInst.imm := LookupTree(decodedInst.selImm, ImmUnion.immSelMap.map( 724 x => { 725 val minBits = x._2.minBitsFromInstr(ctrl_flow.instr) 726 require(minBits.getWidth == x._2.len) 727 x._1 -> minBits 728 } 729 )) 730 731 private val isLs = FuType.isLoadStore(decodedInst.fuType) 732 private val isVls = FuType.isVls(decodedInst.fuType) 733 private val isStore = FuType.isStore(decodedInst.fuType) 734 private val isAMO = FuType.isAMO(decodedInst.fuType) 735 private val isVStore = FuType.isVStore(decodedInst.fuType) 736 private val isBranch = !decodedInst.preDecodeInfo.notCFI || FuType.isJump(decodedInst.fuType) 737 738 decodedInst.commitType := Cat(isLs | isVls, (isStore && !isAMO) | isVStore | isBranch) 739 740 decodedInst.isVset := FuType.isVset(decodedInst.fuType) 741 742 private val needReverseInsts = Seq(VRSUB_VI, VRSUB_VX, VFRDIV_VF, VFRSUB_VF, VFMV_F_S) 743 private val vextInsts = Seq(VZEXT_VF2, VZEXT_VF4, VZEXT_VF8, VSEXT_VF2, VSEXT_VF4, VSEXT_VF8) 744 private val narrowInsts = Seq( 745 VNSRA_WV, VNSRA_WX, VNSRA_WI, VNSRL_WV, VNSRL_WX, VNSRL_WI, 746 VNCLIP_WV, VNCLIP_WX, VNCLIP_WI, VNCLIPU_WV, VNCLIPU_WX, VNCLIPU_WI, 747 ) 748 private val maskDstInsts = Seq( 749 VMADC_VV, VMADC_VX, VMADC_VI, VMADC_VVM, VMADC_VXM, VMADC_VIM, 750 VMSBC_VV, VMSBC_VX, VMSBC_VVM, VMSBC_VXM, 751 VMAND_MM, VMNAND_MM, VMANDN_MM, VMXOR_MM, VMOR_MM, VMNOR_MM, VMORN_MM, VMXNOR_MM, 752 VMSEQ_VV, VMSEQ_VX, VMSEQ_VI, VMSNE_VV, VMSNE_VX, VMSNE_VI, 753 VMSLE_VV, VMSLE_VX, VMSLE_VI, VMSLEU_VV, VMSLEU_VX, VMSLEU_VI, 754 VMSLT_VV, VMSLT_VX, VMSLTU_VV, VMSLTU_VX, 755 VMSGT_VX, VMSGT_VI, VMSGTU_VX, VMSGTU_VI, 756 VMFEQ_VV, VMFEQ_VF, VMFNE_VV, VMFNE_VF, VMFLT_VV, VMFLT_VF, VMFLE_VV, VMFLE_VF, VMFGT_VF, VMFGE_VF, 757 ) 758 private val maskOpInsts = Seq( 759 VMAND_MM, VMNAND_MM, VMANDN_MM, VMXOR_MM, VMOR_MM, VMNOR_MM, VMORN_MM, VMXNOR_MM, 760 ) 761 private val wfflagsInsts = Seq( 762 // opfff 763 FADD_S, FSUB_S, FADD_D, FSUB_D, 764 FEQ_S, FLT_S, FLE_S, FEQ_D, FLT_D, FLE_D, 765 FMIN_S, FMAX_S, FMIN_D, FMAX_D, 766 FMUL_S, FMUL_D, 767 FDIV_S, FDIV_D, FSQRT_S, FSQRT_D, 768 FMADD_S, FMSUB_S, FNMADD_S, FNMSUB_S, FMADD_D, FMSUB_D, FNMADD_D, FNMSUB_D, 769 FSGNJ_S, FSGNJN_S, FSGNJX_S, 770 // opfvv 771 VFADD_VV, VFSUB_VV, VFWADD_VV, VFWSUB_VV, VFWADD_WV, VFWSUB_WV, 772 VFMUL_VV, VFDIV_VV, VFWMUL_VV, 773 VFMACC_VV, VFNMACC_VV, VFMSAC_VV, VFNMSAC_VV, VFMADD_VV, VFNMADD_VV, VFMSUB_VV, VFNMSUB_VV, 774 VFWMACC_VV, VFWNMACC_VV, VFWMSAC_VV, VFWNMSAC_VV, 775 VFSQRT_V, 776 VFMIN_VV, VFMAX_VV, 777 VMFEQ_VV, VMFNE_VV, VMFLT_VV, VMFLE_VV, 778 VFSGNJ_VV, VFSGNJN_VV, VFSGNJX_VV, 779 // opfvf 780 VFADD_VF, VFSUB_VF, VFRSUB_VF, VFWADD_VF, VFWSUB_VF, VFWADD_WF, VFWSUB_WF, 781 VFMUL_VF, VFDIV_VF, VFRDIV_VF, VFWMUL_VF, 782 VFMACC_VF, VFNMACC_VF, VFMSAC_VF, VFNMSAC_VF, VFMADD_VF, VFNMADD_VF, VFMSUB_VF, VFNMSUB_VF, 783 VFWMACC_VF, VFWNMACC_VF, VFWMSAC_VF, VFWNMSAC_VF, 784 VFMIN_VF, VFMAX_VF, 785 VMFEQ_VF, VMFNE_VF, VMFLT_VF, VMFLE_VF, VMFGT_VF, VMFGE_VF, 786 VFSGNJ_VF, VFSGNJN_VF, VFSGNJX_VF, 787 // fcvt & vfcvt 788 FCVT_S_W, FCVT_S_WU, FCVT_S_L, FCVT_S_LU, 789 FCVT_W_S, FCVT_WU_S, FCVT_L_S, FCVT_LU_S, 790 FCVT_D_W, FCVT_D_WU, FCVT_D_L, FCVT_D_LU, 791 FCVT_W_D, FCVT_WU_D, FCVT_L_D, FCVT_LU_D, FCVT_S_D, FCVT_D_S, 792 VFCVT_XU_F_V, VFCVT_X_F_V, VFCVT_RTZ_XU_F_V, VFCVT_RTZ_X_F_V, VFCVT_F_XU_V, VFCVT_F_X_V, 793 VFWCVT_XU_F_V, VFWCVT_X_F_V, VFWCVT_RTZ_XU_F_V, VFWCVT_RTZ_X_F_V, VFWCVT_F_XU_V, VFWCVT_F_X_V, VFWCVT_F_F_V, 794 VFNCVT_XU_F_W, VFNCVT_X_F_W, VFNCVT_RTZ_XU_F_W, VFNCVT_RTZ_X_F_W, VFNCVT_F_XU_W, VFNCVT_F_X_W, VFNCVT_F_F_W, 795 VFNCVT_ROD_F_F_W, VFRSQRT7_V, VFREC7_V, 796 ) 797 decodedInst.wfflags := wfflagsInsts.map(_ === inst.ALL).reduce(_ || _) 798 val fpToVecDecoder = Module(new FPToVecDecoder()) 799 fpToVecDecoder.io.instr := inst.asUInt 800 val isFpToVecInst = fpToVecDecoder.io.vpuCtrl.fpu.isFpToVecInst 801 decodedInst.vpu := 0.U.asTypeOf(decodedInst.vpu) // Todo: Connect vpu decoder 802 when(isFpToVecInst){ 803 decodedInst.vpu := fpToVecDecoder.io.vpuCtrl 804 }.otherwise{ 805 decodedInst.vpu.vill := io.enq.vtype.illegal 806 decodedInst.vpu.vma := io.enq.vtype.vma 807 decodedInst.vpu.vta := io.enq.vtype.vta 808 decodedInst.vpu.vsew := io.enq.vtype.vsew 809 decodedInst.vpu.vlmul := io.enq.vtype.vlmul 810 decodedInst.vpu.vm := inst.VM 811 decodedInst.vpu.nf := inst.NF 812 decodedInst.vpu.veew := inst.WIDTH 813 decodedInst.vpu.isReverse := needReverseInsts.map(_ === inst.ALL).reduce(_ || _) 814 decodedInst.vpu.isExt := vextInsts.map(_ === inst.ALL).reduce(_ || _) 815 val isNarrow = narrowInsts.map(_ === inst.ALL).reduce(_ || _) 816 val isDstMask = maskDstInsts.map(_ === inst.ALL).reduce(_ || _) 817 val isOpMask = maskOpInsts.map(_ === inst.ALL).reduce(_ || _) 818 val isVlx = decodedInst.fuOpType === VlduType.vloxe || decodedInst.fuOpType === VlduType.vluxe 819 val isWritePartVd = decodedInst.uopSplitType === UopSplitType.VEC_VRED || decodedInst.uopSplitType === UopSplitType.VEC_0XV 820 decodedInst.vpu.isNarrow := isNarrow 821 decodedInst.vpu.isDstMask := isDstMask 822 decodedInst.vpu.isOpMask := isOpMask 823 decodedInst.vpu.isDependOldvd := isVppu || isVecOPF || isVStore || (isDstMask && !isOpMask) || isNarrow || isVlx 824 decodedInst.vpu.isWritePartVd := isWritePartVd 825 } 826 827 decodedInst.vlsInstr := isVls 828 829 val uopInfoGen = Module(new UopInfoGen) 830 uopInfoGen.io.in.preInfo.typeOfSplit := decodedInst.uopSplitType 831 uopInfoGen.io.in.preInfo.vsew := decodedInst.vpu.vsew 832 uopInfoGen.io.in.preInfo.vlmul := decodedInst.vpu.vlmul 833 uopInfoGen.io.in.preInfo.vwidth := inst.RM 834 uopInfoGen.io.in.preInfo.vmvn := inst.IMM5_OPIVI(2, 0) 835 uopInfoGen.io.in.preInfo.nf := inst.NF 836 uopInfoGen.io.in.preInfo.isVlsr := decodedInst.fuOpType === VlduType.vlr || decodedInst.fuOpType === VstuType.vsr 837 uopInfoGen.io.in.preInfo.isVlsm := decodedInst.fuOpType === VlduType.vlm || decodedInst.fuOpType === VstuType.vsm 838 io.deq.isComplex := uopInfoGen.io.out.isComplex 839 io.deq.uopInfo.numOfUop := uopInfoGen.io.out.uopInfo.numOfUop 840 io.deq.uopInfo.numOfWB := uopInfoGen.io.out.uopInfo.numOfWB 841 io.deq.uopInfo.lmul := uopInfoGen.io.out.uopInfo.lmul 842 843 io.deq.decodedInst := decodedInst 844 io.deq.decodedInst.rfWen := (decodedInst.ldest =/= 0.U) && decodedInst.rfWen 845 846 // when instruction is not a vector instruction 847 decodedInst.srcType(2) := Mux(!isFpToVecInst, SrcType.vp, SrcType.no) // old vd 848 //------------------------------------------------------------- 849 // Debug Info 850// XSDebug("in: instr=%x pc=%x excepVec=%b crossPageIPFFix=%d\n", 851// io.enq.ctrl_flow.instr, io.enq.ctrl_flow.pc, io.enq.ctrl_flow.exceptionVec.asUInt, 852// io.enq.ctrl_flow.crossPageIPFFix) 853// XSDebug("out: srcType(0)=%b srcType(1)=%b srcType(2)=%b lsrc(0)=%d lsrc(1)=%d lsrc(2)=%d ldest=%d fuType=%b fuOpType=%b\n", 854// io.deq.cf_ctrl.ctrl.srcType(0), io.deq.cf_ctrl.ctrl.srcType(1), io.deq.cf_ctrl.ctrl.srcType(2), 855// io.deq.cf_ctrl.ctrl.lsrc(0), io.deq.cf_ctrl.ctrl.lsrc(1), io.deq.cf_ctrl.ctrl.lsrc(2), 856// io.deq.cf_ctrl.ctrl.ldest, io.deq.cf_ctrl.ctrl.fuType, io.deq.cf_ctrl.ctrl.fuOpType) 857// XSDebug("out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d flushPipe=%d imm=%x\n", 858// io.deq.cf_ctrl.ctrl.rfWen, io.deq.cf_ctrl.ctrl.fpWen, io.deq.cf_ctrl.ctrl.isXSTrap, 859// io.deq.cf_ctrl.ctrl.noSpecExec, io.deq.cf_ctrl.ctrl.blockBackward, io.deq.cf_ctrl.ctrl.flushPipe, 860// io.deq.cf_ctrl.ctrl.imm) 861// XSDebug("out: excepVec=%b\n", io.deq.cf_ctrl.cf.exceptionVec.asUInt) 862} 863