1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions._ 23import freechips.rocketchip.util.uintToBitPat 24import utility._ 25import utils._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.FuType 29import xiangshan.backend.Bundles.{DecodedInst, DynInst, StaticInst} 30 31/** 32 * Abstract trait giving defaults and other relevant values to different Decode constants/ 33 */ 34abstract trait DecodeConstants { 35 // This X should be used only in 1-bit signal. Otherwise, use BitPat("b???") to align with the width of UInt. 36 def X = BitPat("b0") 37 def N = BitPat("b0") 38 def Y = BitPat("b1") 39 def T = true 40 def F = false 41 42 def decodeDefault: List[BitPat] = // illegal instruction 43 // srcType(0) srcType(1) srcType(2) fuType fuOpType rfWen 44 // | | | | | | fpWen 45 // | | | | | | | vecWen 46 // | | | | | | | | isXSTrap 47 // | | | | | | | | | noSpecExec 48 // | | | | | | | | | | blockBackward 49 // | | | | | | | | | | | flushPipe 50 // | | | | | | | | | | | | selImm 51 List(SrcType.X, SrcType.X, SrcType.X, FuType.X, FuOpType.X, N, N, N, N, N, N, N, SelImm.INVALID_INSTR) // Use SelImm to indicate invalid instr 52 53 val decodeArray: Array[(BitPat, XSDecodeBase)] 54 final def table: Array[(BitPat, List[BitPat])] = decodeArray.map(x => (x._1, x._2.generate())) 55} 56 57trait DecodeUnitConstants 58{ 59 // abstract out instruction decode magic numbers 60 val RD_MSB = 11 61 val RD_LSB = 7 62 val RS1_MSB = 19 63 val RS1_LSB = 15 64 val RS2_MSB = 24 65 val RS2_LSB = 20 66 val RS3_MSB = 31 67 val RS3_LSB = 27 68} 69 70/** 71 * Decoded control signals 72 * See xiangshan/package.scala, xiangshan/backend/package.scala, Bundle.scala 73 */ 74 75abstract class XSDecodeBase { 76 def X = BitPat("b?") 77 def N = BitPat("b0") 78 def Y = BitPat("b1") 79 def T = true 80 def F = false 81 def generate() : List[BitPat] 82} 83 84case class XSDecode( 85 src1: BitPat, src2: BitPat, src3: BitPat, 86 fu: Int, fuOp: BitPat, selImm: BitPat, 87 xWen: Boolean = false, 88 fWen: Boolean = false, 89 vWen: Boolean = false, 90 mWen: Boolean = false, 91 xsTrap: Boolean = false, 92 noSpec: Boolean = false, 93 blockBack: Boolean = false, 94 flushPipe: Boolean = false, 95) extends XSDecodeBase { 96 def generate() : List[BitPat] = { 97 List (src1, src2, src3, BitPat(fu.U(FuType.num.W)), fuOp, xWen.B, fWen.B, (vWen || mWen).B, xsTrap.B, noSpec.B, blockBack.B, flushPipe.B, selImm) 98 } 99} 100 101case class FDecode( 102 src1: BitPat, src2: BitPat, src3: BitPat, 103 fu: Int, fuOp: BitPat, selImm: BitPat = SelImm.X, 104 xWen: Boolean = false, 105 fWen: Boolean = false, 106 vWen: Boolean = false, 107 mWen: Boolean = false, 108 xsTrap: Boolean = false, 109 noSpec: Boolean = false, 110 blockBack: Boolean = false, 111 flushPipe: Boolean = false, 112) extends XSDecodeBase { 113 def generate() : List[BitPat] = { 114 XSDecode(src1, src2, src3, fu, fuOp, selImm, xWen, fWen, vWen, mWen, xsTrap, noSpec, blockBack, flushPipe).generate() 115 } 116} 117 118/** 119 * Decode constants for RV64 120 */ 121object X64Decode extends DecodeConstants { 122 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 123 LD -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld , SelImm.IMM_I, xWen = T), 124 LWU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lwu , SelImm.IMM_I, xWen = T), 125 SD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sd , SelImm.IMM_S ), 126 127 SLLI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sll , SelImm.IMM_I, xWen = T), 128 SRLI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srl , SelImm.IMM_I, xWen = T), 129 SRAI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sra , SelImm.IMM_I, xWen = T), 130 131 ADDIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.addw, SelImm.IMM_I, xWen = T), 132 SLLIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sllw, SelImm.IMM_I, xWen = T), 133 SRAIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sraw, SelImm.IMM_I, xWen = T), 134 SRLIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srlw, SelImm.IMM_I, xWen = T), 135 136 ADDW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.addw, SelImm.X , xWen = T), 137 SUBW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.subw, SelImm.X , xWen = T), 138 SLLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sllw, SelImm.X , xWen = T), 139 SRAW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sraw, SelImm.X , xWen = T), 140 SRLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srlw, SelImm.X , xWen = T), 141 142 RORW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rorw, SelImm.X , xWen = T), 143 RORIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.rorw, SelImm.IMM_I, xWen = T), 144 ROLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rolw, SelImm.X , xWen = T), 145 ) 146} 147 148/** 149 * Overall Decode constants 150 */ 151object XDecode extends DecodeConstants { 152 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 153 LW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw , SelImm.IMM_I, xWen = T), 154 LH -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lh , SelImm.IMM_I, xWen = T), 155 LHU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lhu , SelImm.IMM_I, xWen = T), 156 LB -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lb , SelImm.IMM_I, xWen = T), 157 LBU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lbu , SelImm.IMM_I, xWen = T), 158 SW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sw , SelImm.IMM_S ), 159 SH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sh , SelImm.IMM_S ), 160 SB -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sb , SelImm.IMM_S ), 161 LUI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add , SelImm.IMM_U, xWen = T), 162 ADDI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add , SelImm.IMM_I, xWen = T), 163 ANDI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.and , SelImm.IMM_I, xWen = T), 164 ORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.or , SelImm.IMM_I, xWen = T), 165 XORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.xor , SelImm.IMM_I, xWen = T), 166 SLTI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slt , SelImm.IMM_I, xWen = T), 167 SLTIU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sltu, SelImm.IMM_I, xWen = T), 168 SLL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sll , SelImm.X , xWen = T), 169 ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.add , SelImm.X , xWen = T), 170 SUB -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sub , SelImm.X , xWen = T), 171 SLT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.slt , SelImm.X , xWen = T), 172 SLTU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sltu, SelImm.X , xWen = T), 173 AND -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.and , SelImm.X , xWen = T), 174 OR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.or , SelImm.X , xWen = T), 175 XOR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xor , SelImm.X , xWen = T), 176 SRA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sra , SelImm.X , xWen = T), 177 SRL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srl , SelImm.X , xWen = T), 178 179 MUL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mul , SelImm.X, xWen = T), 180 MULH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulh , SelImm.X, xWen = T), 181 MULHU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhu , SelImm.X, xWen = T), 182 MULHSU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhsu, SelImm.X, xWen = T), 183 MULW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulw , SelImm.X, xWen = T), 184 185 DIV -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.div , SelImm.X, xWen = T), 186 DIVU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divu , SelImm.X, xWen = T), 187 REM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.rem , SelImm.X, xWen = T), 188 REMU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remu , SelImm.X, xWen = T), 189 DIVW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divw , SelImm.X, xWen = T), 190 DIVUW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divuw , SelImm.X, xWen = T), 191 REMW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remw , SelImm.X, xWen = T), 192 REMUW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remuw , SelImm.X, xWen = T), 193 194 AUIPC -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.auipc, SelImm.IMM_U , xWen = T), 195 JAL -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jal , SelImm.IMM_UJ, xWen = T), 196 JALR -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jalr , SelImm.IMM_I , xWen = T), 197 BEQ -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.beq , SelImm.IMM_SB ), 198 BNE -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bne , SelImm.IMM_SB ), 199 BGE -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bge , SelImm.IMM_SB ), 200 BGEU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bgeu , SelImm.IMM_SB ), 201 BLT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.blt , SelImm.IMM_SB ), 202 BLTU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bltu , SelImm.IMM_SB ), 203 204 // I-type, the immediate12 holds the CSR register. 205 CSRRW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrt , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 206 CSRRS -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.set , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 207 CSRRC -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clr , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 208 209 CSRRWI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrti, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 210 CSRRSI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.seti, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 211 CSRRCI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clri, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 212 213 EBREAK -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 214 ECALL -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 215 SRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 216 MRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 217 DRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 218 WFI -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.csr, CSROpType.wfi, SelImm.X , xWen = T, noSpec = T, blockBack = T), 219 220 SFENCE_VMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 221 FENCE_I -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fencei, SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 222 FENCE -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fence , SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 223 224 // A-type 225 AMOADD_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 226 AMOXOR_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 227 AMOSWAP_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 228 AMOAND_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 229 AMOOR_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 230 AMOMIN_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 231 AMOMINU_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 232 AMOMAX_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 233 AMOMAXU_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 234 235 AMOADD_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 236 AMOXOR_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 237 AMOSWAP_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 238 AMOAND_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 239 AMOOR_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 240 AMOMIN_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 241 AMOMINU_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 242 AMOMAX_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 243 AMOMAXU_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 244 245 LR_W -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 246 LR_D -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 247 SC_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 248 SC_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 249 250 ANDN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.andn, SelImm.X, xWen = T), 251 ORN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.orn , SelImm.X, xWen = T), 252 XNOR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xnor, SelImm.X, xWen = T), 253 ORC_B -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.orcb, SelImm.X, xWen = T), 254 255 MIN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.min , SelImm.X, xWen = T), 256 MINU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.minu, SelImm.X, xWen = T), 257 MAX -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.max , SelImm.X, xWen = T), 258 MAXU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.maxu, SelImm.X, xWen = T), 259 260 SEXT_B -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sextb, SelImm.X, xWen = T), 261 PACKH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packh, SelImm.X, xWen = T), 262 SEXT_H -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sexth, SelImm.X, xWen = T), 263 PACKW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packw, SelImm.X, xWen = T), 264 BREV8 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.revb , SelImm.X, xWen = T), 265 REV8 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.rev8 , SelImm.X, xWen = T), 266 PACK -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.pack , SelImm.X, xWen = T), 267 268 BSET -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bset, SelImm.X , xWen = T), 269 BSETI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bset, SelImm.IMM_I, xWen = T), 270 BCLR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bclr, SelImm.X , xWen = T), 271 BCLRI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bclr, SelImm.IMM_I, xWen = T), 272 BINV -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.binv, SelImm.X , xWen = T), 273 BINVI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.binv, SelImm.IMM_I, xWen = T), 274 BEXT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bext, SelImm.X , xWen = T), 275 BEXTI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bext, SelImm.IMM_I, xWen = T), 276 277 ROR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.ror, SelImm.X , xWen = T), 278 RORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.ror, SelImm.IMM_I , xWen = T), 279 ROL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rol, SelImm.X , xWen = T), 280 281 SH1ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1add , SelImm.X , xWen = T), 282 SH2ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2add , SelImm.X , xWen = T), 283 SH3ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3add , SelImm.X , xWen = T), 284 SH1ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1adduw, SelImm.X , xWen = T), 285 SH2ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2adduw, SelImm.X , xWen = T), 286 SH3ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3adduw, SelImm.X , xWen = T), 287 ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.adduw , SelImm.X , xWen = T), 288 SLLI_UW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slliuw , SelImm.IMM_I, xWen = T), 289 ) 290} 291 292/** 293 * FP Decode constants 294 */ 295object FpDecode extends DecodeConstants{ 296 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 297 FLW -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw, selImm = SelImm.IMM_I, fWen = T), 298 FLD -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld, selImm = SelImm.IMM_I, fWen = T), 299 FSW -> FDecode(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sw, selImm = SelImm.IMM_S ), 300 FSD -> FDecode(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sd, selImm = SelImm.IMM_S ), 301 302 FCLASS_S-> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 303 FCLASS_D-> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 304 305 FMV_X_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 306 FMV_X_W -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 307 308 FMV_D_X -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 309 FMV_W_X -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 310 311 FSGNJ_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 312 FSGNJ_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 313 FSGNJX_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 314 FSGNJX_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 315 FSGNJN_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 316 FSGNJN_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 317 318 // FP to FP 319 FCVT_S_D -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 320 FCVT_D_S -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 321 322 // Int to FP 323 FCVT_S_W -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 324 FCVT_S_WU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 325 FCVT_S_L -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 326 FCVT_S_LU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 327 328 FCVT_D_W -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 329 FCVT_D_WU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 330 FCVT_D_L -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 331 FCVT_D_LU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 332 333 // FP to Int 334 FCVT_W_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 335 FCVT_WU_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 336 FCVT_L_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 337 FCVT_LU_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 338 339 FCVT_W_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 340 FCVT_WU_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 341 FCVT_L_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 342 FCVT_LU_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 343 344 FEQ_S -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 345 FLT_S -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 346 FLE_S -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 347 348 FEQ_D -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 349 FLT_D -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 350 FLE_D -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 351 352 FMIN_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 353 FMAX_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 354 FMIN_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 355 FMAX_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 356 357 FADD_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 358 FSUB_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 359 FMUL_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 360 FADD_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 361 FSUB_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 362 FMUL_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 363 364 FMADD_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 365 FMSUB_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 366 FNMADD_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 367 FNMSUB_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 368 FMADD_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 369 FMSUB_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 370 FNMADD_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 371 FNMSUB_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 372 ) 373} 374 375/** 376 * Bit Manipulation Decode 377 */ 378object BDecode extends DecodeConstants{ 379 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 380 // Basic bit manipulation 381 CLZ -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.clz, SelImm.X, xWen = T), 382 CTZ -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.ctz, SelImm.X, xWen = T), 383 CPOP -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpop, SelImm.X, xWen = T), 384 XPERM8 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermb, SelImm.X, xWen = T), 385 XPERM4 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermn, SelImm.X, xWen = T), 386 387 CLZW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.clzw, SelImm.X, xWen = T), 388 CTZW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.ctzw, SelImm.X, xWen = T), 389 CPOPW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpopw, SelImm.X, xWen = T), 390 391 CLMUL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmul, SelImm.X, xWen = T), 392 CLMULH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulh, SelImm.X, xWen = T), 393 CLMULR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulr, SelImm.X, xWen = T), 394 395 AES64ES -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64es, SelImm.X , xWen = T), 396 AES64ESM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64esm, SelImm.X , xWen = T), 397 AES64DS -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ds, SelImm.X , xWen = T), 398 AES64DSM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64dsm, SelImm.X , xWen = T), 399 AES64IM -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.aes64im, SelImm.X , xWen = T), 400 AES64KS1I -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.bku, BKUOpType.aes64ks1i, SelImm.IMM_I, xWen = T), 401 AES64KS2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ks2, SelImm.X , xWen = T), 402 SHA256SUM0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum0, SelImm.X , xWen = T), 403 SHA256SUM1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum1, SelImm.X , xWen = T), 404 SHA256SIG0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig0, SelImm.X , xWen = T), 405 SHA256SIG1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig1, SelImm.X , xWen = T), 406 SHA512SUM0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum0, SelImm.X , xWen = T), 407 SHA512SUM1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum1, SelImm.X , xWen = T), 408 SHA512SIG0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig0, SelImm.X , xWen = T), 409 SHA512SIG1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig1, SelImm.X , xWen = T), 410 SM3P0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p0, SelImm.X , xWen = T), 411 SM3P1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p1, SelImm.X , xWen = T), 412 SM4KS0 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks0, SelImm.X , xWen = T), 413 SM4KS1 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks1, SelImm.X , xWen = T), 414 SM4KS2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks2, SelImm.X , xWen = T), 415 SM4KS3 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks3, SelImm.X , xWen = T), 416 SM4ED0 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed0, SelImm.X , xWen = T), 417 SM4ED1 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed1, SelImm.X , xWen = T), 418 SM4ED2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed2, SelImm.X , xWen = T), 419 SM4ED3 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed3, SelImm.X , xWen = T), 420 ) 421} 422 423/** 424 * FP Divide SquareRoot Constants 425 */ 426object FDivSqrtDecode extends DecodeConstants { 427 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 428 FDIV_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T), 429 FDIV_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T), 430 FSQRT_S -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T), 431 FSQRT_D -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T), 432 ) 433} 434 435/** 436 * Svinval extension Constants 437 */ 438object SvinvalDecode extends DecodeConstants { 439 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 440 /* sinval_vma is like sfence.vma , but sinval_vma can be dispatched and issued like normal instructions while sfence.vma 441 * must assure it is the ONLY instrucion executing in backend. 442 */ 443 SINVAL_VMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, SelImm.X), 444 /* sfecne.w.inval is the begin instrucion of a TLB flush which set *noSpecExec* and *blockBackward* signals 445 * so when it comes to dispatch , it will block all instruction after itself until all instrucions ahead of it in rob commit 446 * then dispatch and issue this instrucion to flush sbuffer to dcache 447 * after this instrucion commits , issue following sinval_vma instructions (out of order) to flush TLB 448 */ 449 SFENCE_W_INVAL -> XSDecode(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, SelImm.X, noSpec = T, blockBack = T), 450 /* sfecne.inval.ir is the end instrucion of a TLB flush which set *noSpecExec* *blockBackward* and *flushPipe* signals 451 * so when it comes to dispatch , it will wait until all sinval_vma ahead of it in rob commit 452 * then dispatch and issue this instrucion 453 * when it commit at the head of rob , flush the pipeline since some instrucions have been fetched to ibuffer using old TLB map 454 */ 455 SFENCE_INVAL_IR -> XSDecode(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, SelImm.X, noSpec = T, blockBack = T, flushPipe = T) 456 /* what is Svinval extension ? 457 * -----> sfecne.w.inval 458 * sfence.vma vpn1 -----> sinval_vma vpn1 459 * sfence.vma vpn2 -----> sinval_vma vpn2 460 * -----> sfecne.inval.ir 461 * 462 * sfence.vma should be executed in-order and it flushes the pipeline after committing 463 * we can parallel sfence instrucions with this extension 464 */ 465 ) 466} 467 468/* 469 * CBO decode 470 */ 471object CBODecode extends DecodeConstants { 472 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 473 CBO_ZERO -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_zero , SelImm.IMM_S), 474 CBO_CLEAN -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_clean, SelImm.IMM_S), 475 CBO_FLUSH -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_flush, SelImm.IMM_S), 476 CBO_INVAL -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_inval, SelImm.IMM_S) 477 ) 478} 479 480/** 481 * XiangShan Trap Decode constants 482 */ 483object XSTrapDecode extends DecodeConstants { 484 def TRAP = BitPat("b000000000000?????000000001101011") 485 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 486 TRAP -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add, SelImm.IMM_I, xWen = T, xsTrap = T, noSpec = T, blockBack = T) 487 ) 488} 489 490abstract class Imm(val len: Int) extends Bundle { 491 def toImm32(minBits: UInt): UInt = do_toImm32(minBits(len - 1, 0)) 492 def do_toImm32(minBits: UInt): UInt 493 def minBitsFromInstr(instr: UInt): UInt 494} 495 496case class Imm_I() extends Imm(12) { 497 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits(len - 1, 0), 32) 498 499 override def minBitsFromInstr(instr: UInt): UInt = 500 Cat(instr(31, 20)) 501} 502 503case class Imm_S() extends Imm(12) { 504 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 505 506 override def minBitsFromInstr(instr: UInt): UInt = 507 Cat(instr(31, 25), instr(11, 7)) 508} 509 510case class Imm_B() extends Imm(12) { 511 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 512 513 override def minBitsFromInstr(instr: UInt): UInt = 514 Cat(instr(31), instr(7), instr(30, 25), instr(11, 8)) 515} 516 517case class Imm_U() extends Imm(20){ 518 override def do_toImm32(minBits: UInt): UInt = Cat(minBits(len - 1, 0), 0.U(12.W)) 519 520 override def minBitsFromInstr(instr: UInt): UInt = { 521 instr(31, 12) 522 } 523} 524 525case class Imm_J() extends Imm(20){ 526 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 527 528 override def minBitsFromInstr(instr: UInt): UInt = { 529 Cat(instr(31), instr(19, 12), instr(20), instr(30, 25), instr(24, 21)) 530 } 531} 532 533case class Imm_Z() extends Imm(12 + 5){ 534 override def do_toImm32(minBits: UInt): UInt = minBits 535 536 override def minBitsFromInstr(instr: UInt): UInt = { 537 Cat(instr(19, 15), instr(31, 20)) 538 } 539} 540 541case class Imm_B6() extends Imm(6){ 542 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 543 544 override def minBitsFromInstr(instr: UInt): UInt = { 545 instr(25, 20) 546 } 547} 548 549case class Imm_OPIVIS() extends Imm(5){ 550 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 551 552 override def minBitsFromInstr(instr: UInt): UInt = { 553 instr(19, 15) 554 } 555} 556case class Imm_OPIVIU() extends Imm(5){ 557 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 558 559 override def minBitsFromInstr(instr: UInt): UInt = { 560 instr(19, 15) 561 } 562} 563case class Imm_VSETVLI() extends Imm(11){ 564 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 565 566 override def minBitsFromInstr(instr: UInt): UInt = { 567 instr(30, 20) 568 } 569} 570case class Imm_VSETIVLI() extends Imm(15){ 571 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 572 573 override def minBitsFromInstr(instr: UInt): UInt = { 574 Cat(instr(19, 15), instr(29, 20)) 575 } 576} 577object ImmUnion { 578 val I = Imm_I() 579 val S = Imm_S() 580 val B = Imm_B() 581 val U = Imm_U() 582 val J = Imm_J() 583 val Z = Imm_Z() 584 val B6 = Imm_B6() 585 val OPIVIS = Imm_OPIVIS() 586 val OPIVIU = Imm_OPIVIU() 587 val VSETVLI = Imm_VSETVLI() 588 val VSETIVLI = Imm_VSETIVLI() 589 590 val imms = Seq(I, S, B, U, J, Z, B6, OPIVIS, OPIVIU, VSETVLI, VSETIVLI) 591 val maxLen = imms.maxBy(_.len).len 592 val immSelMap = Seq( 593 SelImm.IMM_I, 594 SelImm.IMM_S, 595 SelImm.IMM_SB, 596 SelImm.IMM_U, 597 SelImm.IMM_UJ, 598 SelImm.IMM_Z, 599 SelImm.IMM_B6, 600 SelImm.IMM_OPIVIS, 601 SelImm.IMM_OPIVIU, 602 SelImm.IMM_VSETVLI, 603 SelImm.IMM_VSETIVLI 604 ).zip(imms) 605 println(s"ImmUnion max len: $maxLen") 606} 607 608case class Imm_LUI_LOAD() { 609 def immFromLuiLoad(lui_imm: UInt, load_imm: UInt): UInt = { 610 val loadImm = load_imm(Imm_I().len - 1, 0) 611 Cat(lui_imm(Imm_U().len - loadImm.getWidth - 1, 0), loadImm) 612 } 613 def getLuiImm(uop: DynInst): UInt = { 614 val loadImmLen = Imm_I().len 615 val imm_u = Cat(uop.psrc(1), uop.psrc(0), uop.imm(ImmUnion.maxLen - 1, loadImmLen)) 616 Imm_U().do_toImm32(imm_u) 617 } 618} 619 620/** 621 * IO bundle for the Decode unit 622 */ 623class DecodeUnitIO(implicit p: Parameters) extends XSBundle { 624 val enq = new Bundle { 625 val ctrlFlow = Input(new StaticInst) 626 } 627// val vconfig = Input(UInt(XLEN.W)) 628 val deq = new Bundle { 629 val decodedInsts = Output(new DecodedInst) 630 } 631 val csrCtrl = Input(new CustomCSRCtrlIO) 632} 633 634/** 635 * Decode unit that takes in a single CtrlFlow and generates a CfCtrl. 636 */ 637class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstants { 638 val io = IO(new DecodeUnitIO) 639 640 val ctrl_flow = io.enq.ctrlFlow // input with RVC Expanded 641 642 val decode_table: Array[(BitPat, List[BitPat])] = XDecode.table ++ 643 FpDecode.table ++ 644 FDivSqrtDecode.table ++ 645 X64Decode.table ++ 646 XSTrapDecode.table ++ 647 BDecode.table ++ 648 CBODecode.table ++ 649 SvinvalDecode.table ++ 650 VecDecoder.table 651 652 require(decode_table.map(_._2.length == 13).reduce(_ && _), "Decode tables have different column size") 653 // assertion for LUI: only LUI should be assigned `selImm === SelImm.IMM_U && fuType === FuType.alu` 654 val luiMatch = (t: Seq[BitPat]) => t(3).value == FuType.alu && t.reverse.head.value == SelImm.IMM_U.litValue 655 val luiTable = decode_table.filter(t => luiMatch(t._2)).map(_._1).distinct 656 assert(luiTable.length == 1 && luiTable.head == LUI, "Conflicts: LUI is determined by FuType and SelImm in Dispatch") 657 658 // output 659 val decodedInst: DecodedInst = Wire(new DecodedInst()).decode(ctrl_flow.instr, decode_table) 660 661 val fpDecoder = Module(new FPDecoder) 662 fpDecoder.io.instr := ctrl_flow.instr 663 decodedInst.fpu := fpDecoder.io.fpCtrl 664 665 decodedInst.connectStaticInst(io.enq.ctrlFlow) 666 667// decodedInst.srcType(3) := DontCare 668// decodedInst.lsrc(3) := DontCare 669 decodedInst.uopIdx := "b11111".U 670 671 val isMove = BitPat("b000000000000_?????_000_?????_0010011") === ctrl_flow.instr 672 decodedInst.isMove := isMove && ctrl_flow.instr(RD_MSB, RD_LSB) =/= 0.U 673 674 // read src1~3 location 675 decodedInst.lsrc(0) := ctrl_flow.instr(RS1_MSB, RS1_LSB) 676 decodedInst.lsrc(1) := ctrl_flow.instr(RS2_MSB, RS2_LSB) 677 decodedInst.lsrc(2) := ctrl_flow.instr(RS3_MSB, RS3_LSB) 678 // read dest location 679 decodedInst.ldest := ctrl_flow.instr(RD_MSB, RD_LSB) 680 681 // fill in exception vector 682 decodedInst.exceptionVec(illegalInstr) := decodedInst.selImm === SelImm.INVALID_INSTR 683 684 when (!io.csrCtrl.svinval_enable) { 685 val base_ii = decodedInst.selImm === SelImm.INVALID_INSTR 686 val sinval = BitPat("b0001011_?????_?????_000_00000_1110011") === ctrl_flow.instr 687 val w_inval = BitPat("b0001100_00000_00000_000_00000_1110011") === ctrl_flow.instr 688 val inval_ir = BitPat("b0001100_00001_00000_000_00000_1110011") === ctrl_flow.instr 689 val svinval_ii = sinval || w_inval || inval_ir 690 decodedInst.exceptionVec(illegalInstr) := base_ii || svinval_ii 691 decodedInst.flushPipe := false.B 692 } 693 694 // fix frflags 695 // fflags zero csrrs rd csr 696 val isFrflags = BitPat("b000000000001_00000_010_?????_1110011") === ctrl_flow.instr 697 when (decodedInst.fuType === FuType.csr.U && isFrflags) { 698 decodedInst.blockBackward := false.B 699 } 700 701 decodedInst.imm := LookupTree(decodedInst.selImm, ImmUnion.immSelMap.map( 702 x => { 703 val minBits = x._2.minBitsFromInstr(ctrl_flow.instr) 704 require(minBits.getWidth == x._2.len) 705 x._1 -> minBits 706 } 707 )) 708 709 decodedInst.isVset := FuType.isInt(decodedInst.fuType) && ALUOpType.isVset(decodedInst.fuOpType) 710 decodedInst.commitType := 0.U // Todo: remove it 711 io.deq.decodedInsts := decodedInst 712 713 decodedInst.vpu := 0.U.asTypeOf(decodedInst.vpu) // Todo: Connect vpu decoder 714 715 //------------------------------------------------------------- 716 // Debug Info 717// XSDebug("in: instr=%x pc=%x excepVec=%b crossPageIPFFix=%d\n", 718// io.enq.ctrl_flow.instr, io.enq.ctrl_flow.pc, io.enq.ctrl_flow.exceptionVec.asUInt, 719// io.enq.ctrl_flow.crossPageIPFFix) 720// XSDebug("out: srcType(0)=%b srcType(1)=%b srcType(2)=%b lsrc(0)=%d lsrc(1)=%d lsrc(2)=%d ldest=%d fuType=%b fuOpType=%b\n", 721// io.deq.cf_ctrl.ctrl.srcType(0), io.deq.cf_ctrl.ctrl.srcType(1), io.deq.cf_ctrl.ctrl.srcType(2), 722// io.deq.cf_ctrl.ctrl.lsrc(0), io.deq.cf_ctrl.ctrl.lsrc(1), io.deq.cf_ctrl.ctrl.lsrc(2), 723// io.deq.cf_ctrl.ctrl.ldest, io.deq.cf_ctrl.ctrl.fuType, io.deq.cf_ctrl.ctrl.fuOpType) 724// XSDebug("out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d flushPipe=%d imm=%x\n", 725// io.deq.cf_ctrl.ctrl.rfWen, io.deq.cf_ctrl.ctrl.fpWen, io.deq.cf_ctrl.ctrl.isXSTrap, 726// io.deq.cf_ctrl.ctrl.noSpecExec, io.deq.cf_ctrl.ctrl.blockBackward, io.deq.cf_ctrl.ctrl.flushPipe, 727// io.deq.cf_ctrl.ctrl.imm) 728// XSDebug("out: excepVec=%b\n", io.deq.cf_ctrl.cf.exceptionVec.asUInt) 729} 730