1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import xiangshan.ExceptionNO.illegalInstr 26import xiangshan._ 27import freechips.rocketchip.rocket.Instructions._ 28 29/** 30 * Abstract trait giving defaults and other relevant values to different Decode constants/ 31 */ 32abstract trait DecodeConstants { 33 // This X should be used only in 1-bit signal. Otherwise, use BitPat("b???") to align with the width of UInt. 34 def X = BitPat("b?") 35 def N = BitPat("b0") 36 def Y = BitPat("b1") 37 38 def decodeDefault: List[BitPat] = // illegal instruction 39 // srcType(0) srcType(1) srcType(2) fuType fuOpType rfWen 40 // | | | | | | fpWen 41 // | | | | | | | isXSTrap 42 // | | | | | | | | noSpecExec 43 // | | | | | | | | | blockBackward 44 // | | | | | | | | | | flushPipe 45 // | | | | | | | | | | | isRVF 46 // | | | | | | | | | | | | selImm 47 List(SrcType.DC, SrcType.DC, SrcType.DC, FuType.alu, ALUOpType.sll, N, N, N, N, N, N, N, SelImm.INVALID_INSTR) // Use SelImm to indicate invalid instr 48 49 val table: Array[(BitPat, List[BitPat])] 50} 51 52trait DecodeUnitConstants 53{ 54 // abstract out instruction decode magic numbers 55 val RD_MSB = 11 56 val RD_LSB = 7 57 val RS1_MSB = 19 58 val RS1_LSB = 15 59 val RS2_MSB = 24 60 val RS2_LSB = 20 61 val RS3_MSB = 31 62 val RS3_LSB = 27 63} 64 65/** 66 * Decoded control signals 67 * See xiangshan/package.scala, xiangshan/backend/package.scala, Bundle.scala 68 */ 69 70/** 71 * Decode constants for RV64 72 */ 73object X64Decode extends DecodeConstants { 74 val table: Array[(BitPat, List[BitPat])] = Array( 75 LD -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.ld, Y, N, N, N, N, N, N, SelImm.IMM_I), 76 LWU -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lwu, Y, N, N, N, N, N, N, SelImm.IMM_I), 77 SD -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.stu, LSUOpType.sd, N, N, N, N, N, N, N, SelImm.IMM_S), 78 79 SLLI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sll, Y, N, N, N, N, N, N, SelImm.IMM_I), 80 SRLI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.srl, Y, N, N, N, N, N, N, SelImm.IMM_I), 81 SRAI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sra, Y, N, N, N, N, N, N, SelImm.IMM_I), 82 83 ADDIW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.addw, Y, N, N, N, N, N, N, SelImm.IMM_I), 84 SLLIW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sllw, Y, N, N, N, N, N, N, SelImm.IMM_I), 85 SRAIW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sraw, Y, N, N, N, N, N, N, SelImm.IMM_I), 86 SRLIW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.srlw, Y, N, N, N, N, N, N, SelImm.IMM_I), 87 88 ADDW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.addw, Y, N, N, N, N, N, N, SelImm.IMM_X), 89 SUBW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.subw, Y, N, N, N, N, N, N, SelImm.IMM_X), 90 SLLW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sllw, Y, N, N, N, N, N, N, SelImm.IMM_X), 91 SRAW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sraw, Y, N, N, N, N, N, N, SelImm.IMM_X), 92 SRLW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.srlw, Y, N, N, N, N, N, N, SelImm.IMM_X), 93 94 RORW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.rorw, Y, N, N, N, N, N, N, SelImm.IMM_X), 95 RORIW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.rorw, Y, N, N, N, N, N, N, SelImm.IMM_I), 96 ROLW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.rolw, Y, N, N, N, N, N, N, SelImm.IMM_X) 97 ) 98} 99 100/** 101 * Overall Decode constants 102 */ 103object XDecode extends DecodeConstants { 104 val table: Array[(BitPat, List[BitPat])] = Array( 105 LW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lw, Y, N, N, N, N, N, N, SelImm.IMM_I), 106 LH -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lh, Y, N, N, N, N, N, N, SelImm.IMM_I), 107 LHU -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lhu, Y, N, N, N, N, N, N, SelImm.IMM_I), 108 LB -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lb, Y, N, N, N, N, N, N, SelImm.IMM_I), 109 LBU -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lbu, Y, N, N, N, N, N, N, SelImm.IMM_I), 110 111 SW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.stu, LSUOpType.sw, N, N, N, N, N, N, N, SelImm.IMM_S), 112 SH -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.stu, LSUOpType.sh, N, N, N, N, N, N, N, SelImm.IMM_S), 113 SB -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.stu, LSUOpType.sb, N, N, N, N, N, N, N, SelImm.IMM_S), 114 115 LUI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, N, SelImm.IMM_U), 116 117 ADDI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, N, SelImm.IMM_I), 118 ANDI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.and, Y, N, N, N, N, N, N, SelImm.IMM_I), 119 ORI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.or, Y, N, N, N, N, N, N, SelImm.IMM_I), 120 XORI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.xor, Y, N, N, N, N, N, N, SelImm.IMM_I), 121 SLTI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.slt, Y, N, N, N, N, N, N, SelImm.IMM_I), 122 SLTIU -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sltu, Y, N, N, N, N, N, N, SelImm.IMM_I), 123 124 SLL -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sll, Y, N, N, N, N, N, N, SelImm.IMM_X), 125 ADD -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, N, SelImm.IMM_X), 126 SUB -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sub, Y, N, N, N, N, N, N, SelImm.IMM_X), 127 SLT -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.slt, Y, N, N, N, N, N, N, SelImm.IMM_X), 128 SLTU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sltu, Y, N, N, N, N, N, N, SelImm.IMM_X), 129 AND -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.and, Y, N, N, N, N, N, N, SelImm.IMM_X), 130 OR -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.or, Y, N, N, N, N, N, N, SelImm.IMM_X), 131 XOR -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.xor, Y, N, N, N, N, N, N, SelImm.IMM_X), 132 SRA -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sra, Y, N, N, N, N, N, N, SelImm.IMM_X), 133 SRL -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.srl, Y, N, N, N, N, N, N, SelImm.IMM_X), 134 135 MUL -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mul, Y, N, N, N, N, N, N, SelImm.IMM_X), 136 MULH -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mulh, Y, N, N, N, N, N, N, SelImm.IMM_X), 137 MULHU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mulhu, Y, N, N, N, N, N, N, SelImm.IMM_X), 138 MULHSU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mulhsu, Y, N, N, N, N, N, N, SelImm.IMM_X), 139 MULW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mulw, Y, N, N, N, N, N, N, SelImm.IMM_X), 140 141 DIV -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.div, Y, N, N, N, N, N, N, SelImm.IMM_X), 142 DIVU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.divu, Y, N, N, N, N, N, N, SelImm.IMM_X), 143 REM -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.rem, Y, N, N, N, N, N, N, SelImm.IMM_X), 144 REMU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.remu, Y, N, N, N, N, N, N, SelImm.IMM_X), 145 DIVW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.divw, Y, N, N, N, N, N, N, SelImm.IMM_X), 146 DIVUW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.divuw, Y, N, N, N, N, N, N, SelImm.IMM_X), 147 REMW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.remw, Y, N, N, N, N, N, N, SelImm.IMM_X), 148 REMUW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.remuw, Y, N, N, N, N, N, N, SelImm.IMM_X), 149 150 AUIPC -> List(SrcType.pc , SrcType.imm, SrcType.DC, FuType.jmp, JumpOpType.auipc, Y, N, N, N, N, N, N, SelImm.IMM_U), 151 JAL -> List(SrcType.pc , SrcType.imm, SrcType.DC, FuType.jmp, JumpOpType.jal, Y, N, N, N, N, N, N, SelImm.IMM_UJ), 152 JALR -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.jmp, JumpOpType.jalr, Y, N, N, N, N, N, N, SelImm.IMM_I), 153 BEQ -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.beq, N, N, N, N, N, N, N, SelImm.IMM_SB), 154 BNE -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bne, N, N, N, N, N, N, N, SelImm.IMM_SB), 155 BGE -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bge, N, N, N, N, N, N, N, SelImm.IMM_SB), 156 BGEU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bgeu, N, N, N, N, N, N, N, SelImm.IMM_SB), 157 BLT -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.blt, N, N, N, N, N, N, N, SelImm.IMM_SB), 158 BLTU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bltu, N, N, N, N, N, N, N, SelImm.IMM_SB), 159 160 // I-type, the immediate12 holds the CSR register. 161 CSRRW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.wrt, Y, N, N, Y, Y, N, N, SelImm.IMM_I), 162 CSRRS -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.set, Y, N, N, Y, Y, N, N, SelImm.IMM_I), 163 CSRRC -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.clr, Y, N, N, Y, Y, N, N, SelImm.IMM_I), 164 165 CSRRWI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.wrti, Y, N, N, Y, Y, N, N, SelImm.IMM_Z), 166 CSRRSI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.seti, Y, N, N, Y, Y, N, N, SelImm.IMM_Z), 167 CSRRCI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.clri, Y, N, N, Y, Y, N, N, SelImm.IMM_Z), 168 169 SFENCE_VMA->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.fence, FenceOpType.sfence, N, N, N, Y, Y, Y, N, SelImm.IMM_X), 170 EBREAK -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, N, SelImm.IMM_I), 171 ECALL -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, N, SelImm.IMM_I), 172 SRET -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, N, SelImm.IMM_I), 173 MRET -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, N, SelImm.IMM_I), 174 DRET -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, N, SelImm.IMM_I), 175 176 WFI -> List(SrcType.pc, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.wfi, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 177 178 FENCE_I -> List(SrcType.pc, SrcType.imm, SrcType.DC, FuType.fence, FenceOpType.fencei, N, N, N, Y, Y, Y, N, SelImm.IMM_X), 179 FENCE -> List(SrcType.pc, SrcType.imm, SrcType.DC, FuType.fence, FenceOpType.fence, N, N, N, Y, Y, Y, N, SelImm.IMM_X), 180 181 // A-type 182 AMOADD_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoadd_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 183 AMOXOR_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoxor_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 184 AMOSWAP_W->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoswap_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 185 AMOAND_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoand_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 186 AMOOR_W -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoor_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 187 AMOMIN_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomin_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 188 AMOMINU_W->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amominu_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 189 AMOMAX_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomax_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 190 AMOMAXU_W->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomaxu_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 191 192 AMOADD_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoadd_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 193 AMOXOR_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoxor_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 194 AMOSWAP_D->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoswap_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 195 AMOAND_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoand_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 196 AMOOR_D -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoor_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 197 AMOMIN_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomin_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 198 AMOMINU_D->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amominu_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 199 AMOMAX_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomax_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 200 AMOMAXU_D->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomaxu_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 201 202 LR_W -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.mou, LSUOpType.lr_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 203 LR_D -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.mou, LSUOpType.lr_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 204 SC_W -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.sc_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 205 SC_D -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.sc_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 206 207 ANDN -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.andn, Y, N, N, N, N, N, N, SelImm.IMM_X), 208 ORN -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.orn, Y, N, N, N, N, N, N, SelImm.IMM_X), 209 XNOR -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.xnor, Y, N, N, N, N, N, N, SelImm.IMM_X), 210 ORC_B -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.alu, ALUOpType.orcb, Y, N, N, N, N, N, N, SelImm.IMM_X), 211 212 MIN -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.min, Y, N, N, N, N, N, N, SelImm.IMM_X), 213 MINU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.minu, Y, N, N, N, N, N, N, SelImm.IMM_X), 214 MAX -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.max, Y, N, N, N, N, N, N, SelImm.IMM_X), 215 MAXU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.maxu, Y, N, N, N, N, N, N, SelImm.IMM_X), 216 217 SEXT_B -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.alu, ALUOpType.sextb, Y, N, N, N, N, N, N, SelImm.IMM_X), 218 PACKH -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.packh, Y, N, N, N, N, N, N, SelImm.IMM_X), 219 SEXT_H -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.alu, ALUOpType.sexth, Y, N, N, N, N, N, N, SelImm.IMM_X), 220 PACKW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.packw, Y, N, N, N, N, N, N, SelImm.IMM_X), 221 BREV8 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.alu, ALUOpType.revb, Y, N, N, N, N, N, N, SelImm.IMM_X), 222 REV8 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.alu, ALUOpType.rev8, Y, N, N, N, N, N, N, SelImm.IMM_X), 223 PACK -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.pack, Y, N, N, N, N, N, N, SelImm.IMM_X), 224 225 BSET -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bset, Y, N, N, N, N, N, N, SelImm.IMM_X), 226 BSETI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.bset, Y, N, N, N, N, N, N, SelImm.IMM_I), 227 BCLR -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bclr, Y, N, N, N, N, N, N, SelImm.IMM_X), 228 BCLRI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.bclr, Y, N, N, N, N, N, N, SelImm.IMM_I), 229 BINV -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.binv, Y, N, N, N, N, N, N, SelImm.IMM_X), 230 BINVI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.binv, Y, N, N, N, N, N, N, SelImm.IMM_I), 231 BEXT -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bext, Y, N, N, N, N, N, N, SelImm.IMM_X), 232 BEXTI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.bext, Y, N, N, N, N, N, N, SelImm.IMM_I), 233 234 ROR -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.ror, Y, N, N, N, N, N, N, SelImm.IMM_X), 235 RORI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.ror, Y, N, N, N, N, N, N, SelImm.IMM_I), 236 ROL -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.rol, Y, N, N, N, N, N, N, SelImm.IMM_X), 237 238 SH1ADD -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sh1add, Y, N, N, N, N, N, N, SelImm.IMM_X), 239 SH2ADD -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sh2add, Y, N, N, N, N, N, N, SelImm.IMM_X), 240 SH3ADD -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sh3add, Y, N, N, N, N, N, N, SelImm.IMM_X), 241 SH1ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sh1adduw, Y, N, N, N, N, N, N, SelImm.IMM_X), 242 SH2ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sh2adduw, Y, N, N, N, N, N, N, SelImm.IMM_X), 243 SH3ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sh3adduw, Y, N, N, N, N, N, N, SelImm.IMM_X), 244 ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.adduw, Y, N, N, N, N, N, N, SelImm.IMM_X), 245 SLLI_UW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.slliuw, Y, N, N, N, N, N, N, SelImm.IMM_I) 246 ) 247} 248 249/** 250 * FP Decode constants 251 */ 252object FDecode extends DecodeConstants{ 253 val table: Array[(BitPat, List[BitPat])] = Array( 254 255 FLW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lw, N, Y, N, N, N, N, Y, SelImm.IMM_I), 256 FLD -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.ld, N, Y, N, N, N, N, N, SelImm.IMM_I), 257 FSW -> List(SrcType.reg, SrcType.fp, SrcType.DC, FuType.stu, LSUOpType.sw, N, N, N, N, N, N, Y, SelImm.IMM_S), 258 FSD -> List(SrcType.reg, SrcType.fp, SrcType.DC, FuType.stu, LSUOpType.sd, N, N, N, N, N, N, N, SelImm.IMM_S), 259 260 FCLASS_S-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), 261 FCLASS_D-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), 262 263 FMV_D_X -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 264 FMV_X_D -> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), 265 FMV_X_W -> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), 266 FMV_W_X -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 267 268 FSGNJ_S -> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 269 FSGNJ_D -> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 270 FSGNJX_S-> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 271 FSGNJX_D-> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 272 FSGNJN_S-> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 273 FSGNJN_D-> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 274 275 // FP to FP 276 FCVT_S_D-> List(SrcType.fp, SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 277 FCVT_D_S-> List(SrcType.fp, SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 278 279 // Int to FP 280 FCVT_S_W-> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 281 FCVT_S_WU->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 282 FCVT_S_L-> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 283 FCVT_S_LU->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 284 285 FCVT_D_W-> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 286 FCVT_D_WU->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 287 FCVT_D_L-> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 288 FCVT_D_LU->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 289 290 // FP to Int 291 FCVT_W_S-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), 292 FCVT_WU_S->List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), 293 FCVT_L_S-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), 294 FCVT_LU_S->List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), 295 296 FCVT_W_D-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), 297 FCVT_WU_D->List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), 298 FCVT_L_D-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), 299 FCVT_LU_D->List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), 300 301 // "fp_single" is used for wb_data formatting (and debugging) 302 FEQ_S ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), 303 FLT_S ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), 304 FLE_S ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), 305 306 FEQ_D ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), 307 FLT_D ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), 308 FLE_D ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), 309 310 FMIN_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 311 FMAX_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 312 FMIN_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 313 FMAX_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 314 315 FADD_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 316 FSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 317 FMUL_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 318 FADD_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 319 FSUB_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 320 FMUL_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 321 322 FMADD_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 323 FMSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 324 FNMADD_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 325 FNMSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 326 FMADD_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 327 FMSUB_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 328 FNMADD_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 329 FNMSUB_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X) 330 ) 331} 332 333/** 334 * Bit Manipulation Decode 335 */ 336object BDecode extends DecodeConstants{ 337 val table: Array[(BitPat, List[BitPat])] = Array( 338 // Basic bit manipulation 339 CLZ -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.clz, Y, N, N, N, N, N, N, SelImm.IMM_X), 340 CTZ -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.ctz, Y, N, N, N, N, N, N, SelImm.IMM_X), 341 CPOP -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.cpop, Y, N, N, N, N, N, N, SelImm.IMM_X), 342 XPERM8 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.xpermb, Y, N, N, N, N, N, N, SelImm.IMM_X), 343 XPERM4 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.xpermn, Y, N, N, N, N, N, N, SelImm.IMM_X), 344 345 CLZW -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.clzw, Y, N, N, N, N, N, N, SelImm.IMM_X), 346 CTZW -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.ctzw, Y, N, N, N, N, N, N, SelImm.IMM_X), 347 CPOPW -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.cpopw, Y, N, N, N, N, N, N, SelImm.IMM_X), 348 349 CLMUL -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.clmul, Y, N, N, N, N, N, N, SelImm.IMM_X), 350 CLMULH -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.clmulh, Y, N, N, N, N, N, N, SelImm.IMM_X), 351 CLMULR -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.clmulr, Y, N, N, N, N, N, N, SelImm.IMM_X), 352 353 AES64ES -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.aes64es, Y, N, N, N, N, N, N, SelImm.IMM_X), 354 AES64ESM -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.aes64esm, Y, N, N, N, N, N, N, SelImm.IMM_X), 355 AES64DS -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.aes64ds, Y, N, N, N, N, N, N, SelImm.IMM_X), 356 AES64DSM -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.aes64dsm, Y, N, N, N, N, N, N, SelImm.IMM_X), 357 AES64IM -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.aes64im, Y, N, N, N, N, N, N, SelImm.IMM_X), 358 AES64KS1I -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.bku, BKUOpType.aes64ks1i, Y, N, N, N, N, N, N, SelImm.IMM_I), 359 AES64KS2 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.aes64ks2, Y, N, N, N, N, N, N, SelImm.IMM_X), 360 SHA256SUM0 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha256sum0, Y, N, N, N, N, N, N, SelImm.IMM_X), 361 SHA256SUM1 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha256sum1, Y, N, N, N, N, N, N, SelImm.IMM_X), 362 SHA256SIG0 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha256sig0, Y, N, N, N, N, N, N, SelImm.IMM_X), 363 SHA256SIG1 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha256sig1, Y, N, N, N, N, N, N, SelImm.IMM_X), 364 SHA512SUM0 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha512sum0, Y, N, N, N, N, N, N, SelImm.IMM_X), 365 SHA512SUM1 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha512sum1, Y, N, N, N, N, N, N, SelImm.IMM_X), 366 SHA512SIG0 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha512sig0, Y, N, N, N, N, N, N, SelImm.IMM_X), 367 SHA512SIG1 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha512sig1, Y, N, N, N, N, N, N, SelImm.IMM_X), 368 SM3P0 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sm3p0, Y, N, N, N, N, N, N, SelImm.IMM_X), 369 SM3P1 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sm3p1, Y, N, N, N, N, N, N, SelImm.IMM_X), 370 SM4KS0 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ks0, Y, N, N, N, N, N, N, SelImm.IMM_X), 371 SM4KS1 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ks1, Y, N, N, N, N, N, N, SelImm.IMM_X), 372 SM4KS2 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ks2, Y, N, N, N, N, N, N, SelImm.IMM_X), 373 SM4KS3 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ks3, Y, N, N, N, N, N, N, SelImm.IMM_X), 374 SM4ED0 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ed0, Y, N, N, N, N, N, N, SelImm.IMM_X), 375 SM4ED1 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ed1, Y, N, N, N, N, N, N, SelImm.IMM_X), 376 SM4ED2 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ed2, Y, N, N, N, N, N, N, SelImm.IMM_X), 377 SM4ED3 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ed3, Y, N, N, N, N, N, N, SelImm.IMM_X), 378 ) 379} 380 381/** 382 * FP Divide SquareRoot Constants 383 */ 384object FDivSqrtDecode extends DecodeConstants { 385 val table: Array[(BitPat, List[BitPat])] = Array( 386 FDIV_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 387 FDIV_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), 388 FSQRT_S ->List(SrcType.fp, SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), 389 FSQRT_D ->List(SrcType.fp, SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X) 390 ) 391} 392 393/** 394 * Svinval extension Constants 395 */ 396object SvinvalDecode extends DecodeConstants { 397 val table: Array[(BitPat, List[BitPat])] = Array( 398 /* sinval_vma is like sfence.vma , but sinval_vma can be dispatched and issued like normal instructions while sfence.vma 399 * must assure it is the ONLY instrucion executing in backend. 400 */ 401 SINVAL_VMA ->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.fence, FenceOpType.sfence, N, N, N, N, N, N, N, SelImm.IMM_X), 402 /* sfecne.w.inval is the begin instrucion of a TLB flush which set *noSpecExec* and *blockBackward* signals 403 * so when it comes to dispatch , it will block all instruction after itself until all instrucions ahead of it in rob commit 404 * then dispatch and issue this instrucion to flush sbuffer to dcache 405 * after this instrucion commits , issue following sinval_vma instructions (out of order) to flush TLB 406 */ 407 SFENCE_W_INVAL ->List(SrcType.DC, SrcType.DC, SrcType.DC, FuType.fence, FenceOpType.nofence, N, N, N, Y, Y, N, N, SelImm.IMM_X), 408 /* sfecne.inval.ir is the end instrucion of a TLB flush which set *noSpecExec* *blockBackward* and *flushPipe* signals 409 * so when it comes to dispatch , it will wait until all sinval_vma ahead of it in rob commit 410 * then dispatch and issue this instrucion 411 * when it commit at the head of rob , flush the pipeline since some instrucions have been fetched to ibuffer using old TLB map 412 */ 413 SFENCE_INVAL_IR ->List(SrcType.DC, SrcType.DC, SrcType.DC, FuType.fence, FenceOpType.nofence, N, N, N, Y, Y, Y, N, SelImm.IMM_X) 414 /* what is Svinval extension ? 415 * -----> sfecne.w.inval 416 * sfence.vma vpn1 -----> sinval_vma vpn1 417 * sfence.vma vpn2 -----> sinval_vma vpn2 418 * -----> sfecne.inval.ir 419 * 420 * sfence.vma should be executed in-order and it flushes the pipeline after committing 421 * we can parallel sfence instrucions with this extension 422 */ 423 ) 424} 425/* 426 * CBO decode 427 */ 428object CBODecode extends DecodeConstants { 429 val table: Array[(BitPat, List[BitPat])] = Array( 430 CBO_ZERO -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.stu, LSUOpType.cbo_zero , N, N, N, N, N, N, N, SelImm.IMM_S), 431 CBO_CLEAN -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.stu, LSUOpType.cbo_clean, N, N, N, N, N, N, N, SelImm.IMM_S), 432 CBO_FLUSH -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.stu, LSUOpType.cbo_flush, N, N, N, N, N, N, N, SelImm.IMM_S), 433 CBO_INVAL -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.stu, LSUOpType.cbo_inval, N, N, N, N, N, N, N, SelImm.IMM_S) 434 ) 435} 436 437/** 438 * XiangShan Trap Decode constants 439 */ 440object XSTrapDecode extends DecodeConstants { 441 def TRAP = BitPat("b000000000000?????000000001101011") 442 // calculate as ADDI => addi zero, a0, 0 443 // replace rs '?????' with '01010'(a0) in decode stage 444 def lsrc1 = "b01010".U // $a0 445 val table: Array[(BitPat, List[BitPat])] = Array( 446 TRAP -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.add, Y, N, Y, Y, Y, N, N, SelImm.IMM_I) 447 ) 448} 449 450//object Imm32Gen { 451// def apply(sel: UInt, inst: UInt) = { 452// val sign = Mux(sel === SelImm.IMM_Z, 0.S, inst(31).asSInt) 453// val b30_20 = Mux(sel === SelImm.IMM_U, inst(30,20).asSInt, sign) 454// val b19_12 = Mux(sel =/= SelImm.IMM_U && sel =/= SelImm.IMM_UJ, sign, inst(19,12).asSInt) 455// val b11 = Mux(sel === SelImm.IMM_U || sel === SelImm.IMM_Z, 0.S, 456// Mux(sel === SelImm.IMM_UJ, inst(20).asSInt, 457// Mux(sel === SelImm.IMM_SB, inst(7).asSInt, sign))) 458// val b10_5 = Mux(sel === SelImm.IMM_U || sel === SelImm.IMM_Z, 0.U(1.W), inst(30,25)) 459// val b4_1 = Mux(sel === SelImm.IMM_U, 0.U(1.W), 460// Mux(sel === SelImm.IMM_S || sel === SelImm.IMM_SB, inst(11,8), 461// Mux(sel === SelImm.IMM_Z, inst(19,16), inst(24,21)))) 462// val b0 = Mux(sel === SelImm.IMM_S, inst(7), 463// Mux(sel === SelImm.IMM_I, inst(20), 464// Mux(sel === SelImm.IMM_Z, inst(15), 0.U(1.W)))) 465// 466// Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0) 467// } 468//} 469 470abstract class Imm(val len: Int) extends Bundle { 471 def toImm32(minBits: UInt): UInt = do_toImm32(minBits(len - 1, 0)) 472 def do_toImm32(minBits: UInt): UInt 473 def minBitsFromInstr(instr: UInt): UInt 474} 475 476case class Imm_I() extends Imm(12) { 477 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits(len - 1, 0), 32) 478 479 override def minBitsFromInstr(instr: UInt): UInt = 480 Cat(instr(31, 20)) 481} 482 483case class Imm_S() extends Imm(12) { 484 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 485 486 override def minBitsFromInstr(instr: UInt): UInt = 487 Cat(instr(31, 25), instr(11, 7)) 488} 489 490case class Imm_B() extends Imm(12) { 491 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 492 493 override def minBitsFromInstr(instr: UInt): UInt = 494 Cat(instr(31), instr(7), instr(30, 25), instr(11, 8)) 495} 496 497case class Imm_U() extends Imm(20){ 498 override def do_toImm32(minBits: UInt): UInt = Cat(minBits(len - 1, 0), 0.U(12.W)) 499 500 override def minBitsFromInstr(instr: UInt): UInt = { 501 instr(31, 12) 502 } 503} 504 505case class Imm_J() extends Imm(20){ 506 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 507 508 override def minBitsFromInstr(instr: UInt): UInt = { 509 Cat(instr(31), instr(19, 12), instr(20), instr(30, 25), instr(24, 21)) 510 } 511} 512 513case class Imm_Z() extends Imm(12 + 5){ 514 override def do_toImm32(minBits: UInt): UInt = minBits 515 516 override def minBitsFromInstr(instr: UInt): UInt = { 517 Cat(instr(19, 15), instr(31, 20)) 518 } 519} 520 521case class Imm_B6() extends Imm(6){ 522 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 523 524 override def minBitsFromInstr(instr: UInt): UInt = { 525 instr(25, 20) 526 } 527} 528 529object ImmUnion { 530 val I = Imm_I() 531 val S = Imm_S() 532 val B = Imm_B() 533 val U = Imm_U() 534 val J = Imm_J() 535 val Z = Imm_Z() 536 val B6 = Imm_B6() 537 val imms = Seq(I, S, B, U, J, Z, B6) 538 val maxLen = imms.maxBy(_.len).len 539 val immSelMap = Seq( 540 SelImm.IMM_I, 541 SelImm.IMM_S, 542 SelImm.IMM_SB, 543 SelImm.IMM_U, 544 SelImm.IMM_UJ, 545 SelImm.IMM_Z, 546 SelImm.IMM_B6 547 ).zip(imms) 548 println(s"ImmUnion max len: $maxLen") 549} 550 551case class Imm_LUI_LOAD() { 552 def immFromLuiLoad(lui_imm: UInt, load_imm: UInt): UInt = { 553 val loadImm = load_imm(Imm_I().len - 1, 0) 554 Cat(lui_imm(Imm_U().len - loadImm.getWidth - 1, 0), loadImm) 555 } 556 def getLuiImm(uop: MicroOp): UInt = { 557 val loadImmLen = Imm_I().len 558 val imm_u = Cat(uop.psrc(1), uop.psrc(0), uop.ctrl.imm(ImmUnion.maxLen - 1, loadImmLen)) 559 Imm_U().do_toImm32(imm_u) 560 } 561} 562 563/** 564 * IO bundle for the Decode unit 565 */ 566class DecodeUnitIO(implicit p: Parameters) extends XSBundle { 567 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 568 val deq = new Bundle { val cf_ctrl = Output(new CfCtrl) } 569 val csrCtrl = Input(new CustomCSRCtrlIO) 570} 571 572/** 573 * Decode unit that takes in a single CtrlFlow and generates a CfCtrl. 574 */ 575class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstants { 576 val io = IO(new DecodeUnitIO) 577 578 val ctrl_flow = Wire(new CtrlFlow) // input with RVC Expanded 579 val cf_ctrl = Wire(new CfCtrl) 580 581 ctrl_flow := io.enq.ctrl_flow 582 583 val decode_table = XDecode.table ++ 584 FDecode.table ++ 585 FDivSqrtDecode.table ++ 586 X64Decode.table ++ 587 XSTrapDecode.table ++ 588 BDecode.table ++ 589 CBODecode.table ++ 590 SvinvalDecode.table 591 // assertion for LUI: only LUI should be assigned `selImm === SelImm.IMM_U && fuType === FuType.alu` 592 val luiMatch = (t: Seq[BitPat]) => t(3).value == FuType.alu.litValue && t.reverse.head.value == SelImm.IMM_U.litValue 593 val luiTable = decode_table.filter(t => luiMatch(t._2)).map(_._1).distinct 594 assert(luiTable.length == 1 && luiTable.head == LUI, "Conflicts: LUI is determined by FuType and SelImm in Dispatch") 595 596 // output 597 cf_ctrl.cf := ctrl_flow 598 val cs = Wire(new CtrlSignals()).decode(ctrl_flow.instr, decode_table) 599 cs.singleStep := false.B 600 cs.replayInst := false.B 601 602 val fpDecoder = Module(new FPDecoder) 603 fpDecoder.io.instr := ctrl_flow.instr 604 cs.fpu := fpDecoder.io.fpCtrl 605 606 val isMove = BitPat("b000000000000_?????_000_?????_0010011") === ctrl_flow.instr 607 cs.isMove := isMove && ctrl_flow.instr(RD_MSB, RD_LSB) =/= 0.U 608 609 // read src1~3 location 610 cs.lsrc(0) := ctrl_flow.instr(RS1_MSB, RS1_LSB) 611 cs.lsrc(1) := ctrl_flow.instr(RS2_MSB, RS2_LSB) 612 cs.lsrc(2) := ctrl_flow.instr(RS3_MSB, RS3_LSB) 613 // read dest location 614 cs.ldest := ctrl_flow.instr(RD_MSB, RD_LSB) 615 616 // fill in exception vector 617 cf_ctrl.cf.exceptionVec := io.enq.ctrl_flow.exceptionVec 618 cf_ctrl.cf.exceptionVec(illegalInstr) := cs.selImm === SelImm.INVALID_INSTR 619 620 when (!io.csrCtrl.svinval_enable) { 621 val base_ii = cs.selImm === SelImm.INVALID_INSTR 622 val sinval = BitPat("b0001011_?????_?????_000_00000_1110011") === ctrl_flow.instr 623 val w_inval = BitPat("b0001100_00000_00000_000_00000_1110011") === ctrl_flow.instr 624 val inval_ir = BitPat("b0001100_00001_00000_000_00000_1110011") === ctrl_flow.instr 625 val svinval_ii = sinval || w_inval || inval_ir 626 cf_ctrl.cf.exceptionVec(illegalInstr) := base_ii || svinval_ii 627 cs.flushPipe := false.B 628 } 629 630 // fix frflags 631 // fflags zero csrrs rd csr 632 val isFrflags = BitPat("b000000000001_00000_010_?????_1110011") === ctrl_flow.instr 633 when (cs.fuType === FuType.csr && isFrflags) { 634 cs.blockBackward := false.B 635 } 636 637 // fix isXSTrap 638 when (cs.isXSTrap) { 639 cs.lsrc(0) := XSTrapDecode.lsrc1 640 } 641 642 //to selectout prefetch.r/prefetch.w 643 val isORI = BitPat("b?????????????????110?????0010011") === ctrl_flow.instr 644 when(isORI && io.csrCtrl.soft_prefetch_enable) { 645 // TODO: add CSR based Zicbop config 646 when(cs.ldest === 0.U) { 647 cs.selImm := SelImm.IMM_S 648 cs.fuType := FuType.ldu 649 when(cs.lsrc(1) === "b00001".U) { 650 cs.fuOpType := LSUOpType.prefetch_r 651 }.otherwise { 652 cs.fuOpType := LSUOpType.prefetch_w 653 } 654 } 655 } 656 657 cs.imm := LookupTree(cs.selImm, ImmUnion.immSelMap.map( 658 x => { 659 val minBits = x._2.minBitsFromInstr(ctrl_flow.instr) 660 require(minBits.getWidth == x._2.len) 661 x._1 -> minBits 662 } 663 )) 664 665 cf_ctrl.ctrl := cs 666 667 // TODO: do we still need this? 668 // fix ret and call 669// when (cs.fuType === FuType.jmp) { 670// def isLink(reg: UInt) = (reg === 1.U || reg === 5.U) 671// when (isLink(cs.ldest) && cs.fuOpType === JumpOpType.jal) { cf_ctrl.ctrl.fuOpType := JumpOpType.call } 672// when (cs.fuOpType === JumpOpType.jalr) { 673// when (isLink(cs.lsrc(0))) { cf_ctrl.ctrl.fuOpType := JumpOpType.ret } 674// when (isLink(cs.ldest)) { cf_ctrl.ctrl.fuOpType := JumpOpType.call } 675// } 676// } 677 678 io.deq.cf_ctrl := cf_ctrl 679 680 //------------------------------------------------------------- 681 // Debug Info 682 XSDebug("in: instr=%x pc=%x excepVec=%b intrVec=%b crossPageIPFFix=%d\n", 683 io.enq.ctrl_flow.instr, io.enq.ctrl_flow.pc, io.enq.ctrl_flow.exceptionVec.asUInt, 684 io.enq.ctrl_flow.intrVec.asUInt, io.enq.ctrl_flow.crossPageIPFFix) 685 XSDebug("out: srcType(0)=%b srcType(1)=%b srcType(2)=%b lsrc(0)=%d lsrc(1)=%d lsrc(2)=%d ldest=%d fuType=%b fuOpType=%b\n", 686 io.deq.cf_ctrl.ctrl.srcType(0), io.deq.cf_ctrl.ctrl.srcType(1), io.deq.cf_ctrl.ctrl.srcType(2), 687 io.deq.cf_ctrl.ctrl.lsrc(0), io.deq.cf_ctrl.ctrl.lsrc(1), io.deq.cf_ctrl.ctrl.lsrc(2), 688 io.deq.cf_ctrl.ctrl.ldest, io.deq.cf_ctrl.ctrl.fuType, io.deq.cf_ctrl.ctrl.fuOpType) 689 XSDebug("out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d flushPipe=%d isRVF=%d imm=%x\n", 690 io.deq.cf_ctrl.ctrl.rfWen, io.deq.cf_ctrl.ctrl.fpWen, io.deq.cf_ctrl.ctrl.isXSTrap, 691 io.deq.cf_ctrl.ctrl.noSpecExec, io.deq.cf_ctrl.ctrl.blockBackward, io.deq.cf_ctrl.ctrl.flushPipe, 692 io.deq.cf_ctrl.ctrl.isRVF, io.deq.cf_ctrl.ctrl.imm) 693 XSDebug("out: excepVec=%b intrVec=%b\n", 694 io.deq.cf_ctrl.cf.exceptionVec.asUInt, io.deq.cf_ctrl.cf.intrVec.asUInt) 695} 696