1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig._ 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 var needLoadDependency: Boolean = false 32 // used in bypass to select data of exu output 33 var exuIdx: Int = -1 34 var backendParam: BackendParams = null 35 36 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 37 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 38 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 39 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 40 val numV0Src: Int = fuConfigs.map(_.numV0Src).max 41 val numVlSrc: Int = fuConfigs.map(_.numVlSrc).max 42 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 43 val numSrc: Int = fuConfigs.map(_.numSrc).max 44 val destDataBitsMax: Int = fuConfigs.map(_.destDataBits).max 45 val srcDataBitsMax: Int = fuConfigs.map(x => x.srcDataBits.getOrElse(x.destDataBits)).max 46 val readIntRf: Boolean = numIntSrc > 0 47 val readFpRf: Boolean = numFpSrc > 0 48 val readVecRf: Boolean = numVecSrc > 0 49 val readVfRf: Boolean = numVfSrc > 0 50 val readVlRf: Boolean = numVlSrc > 0 51 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 52 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 53 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 54 val writeV0Rf: Boolean = fuConfigs.map(_.writeV0Rf).reduce(_ || _) 55 val writeVlRf: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 56 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 57 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 58 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 59 val needV0Wen: Boolean = fuConfigs.map(_.needV0Wen).reduce(_ || _) 60 val needVlWen: Boolean = fuConfigs.map(_.needVlWen).reduce(_ || _) 61 val needOg2: Boolean = fuConfigs.map(_.needOg2).reduce(_ || _) 62 val writeVfRf: Boolean = writeVecRf 63 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 64 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 65 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 66 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 67 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 68 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 69 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 70 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 71 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 72 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 73 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 74 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 75 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 76 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 77 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 78 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 79 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 80 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 81 val writeVConfig: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 82 val writeVType: Boolean = fuConfigs.map(_.writeVType).reduce(_ || _) 83 val needCriticalErrors: Boolean = fuConfigs.map(_.needCriticalErrors).reduce(_ || _) 84 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 85 86 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 87 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 88 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 89 90 def needReadRegCache: Boolean = isIntExeUnit || isMemExeUnit && readIntRf 91 def needWriteRegCache: Boolean = isIntExeUnit && isIQWakeUpSource || isMemExeUnit && isIQWakeUpSource && readIntRf 92 93 def numCopySrc: Int = fuConfigs.map(x => if(x.srcNeedCopy) 1 else 0).reduce(_ + _) 94 def idxCopySrc: Seq[Int] = (0 until fuConfigs.length).map { idx => 95 fuConfigs.take(idx + 1).map(x => if(x.srcNeedCopy) 1 else 0).reduce(_ + _) - 1 96 } 97 98 // exu writeback: 0 normalout; 1 intout; 2 fpout; 3 vecout 99 val wbNeedIntWen : Boolean = writeIntRf && !isMemExeUnit 100 val wbNeedFpWen : Boolean = writeFpRf && !isMemExeUnit 101 val wbNeedVecWen : Boolean = writeVecRf && !isMemExeUnit 102 val wbNeedV0Wen : Boolean = writeV0Rf && !isMemExeUnit 103 val wbNeedVlWen : Boolean = writeVlRf && !isMemExeUnit 104 val wbPathNum: Int = Seq(wbNeedIntWen, wbNeedFpWen, wbNeedVecWen, wbNeedV0Wen, wbNeedVlWen).count(_ == true) + 1 105 val wbNeeds = Seq( 106 ("int", wbNeedIntWen), 107 ("fp", wbNeedFpWen), 108 ("vec", wbNeedVecWen), 109 ("v0", wbNeedV0Wen), 110 ("vl", wbNeedVlWen) 111 ) 112 val wbIndexeds = wbNeeds.filter(_._2).zipWithIndex.map { 113 case ((label, _), index) => (label, index + 1) 114 }.toMap 115 val wbIntIndex: Int = wbIndexeds.getOrElse("int", 0) 116 val wbFpIndex : Int = wbIndexeds.getOrElse("fp", 0) 117 val wbVecIndex: Int = wbIndexeds.getOrElse("vec", 0) 118 val wbV0Index : Int = wbIndexeds.getOrElse("v0" , 0) 119 val wbVlIndex : Int = wbIndexeds.getOrElse("vl" , 0) 120 val wbIndex: Seq[Int] = Seq(wbIntIndex, wbFpIndex, wbVecIndex, wbV0Index, wbVlIndex) 121 122 123 def copyNum: Int = { 124 val setIQ = mutable.Set[IssueBlockParams]() 125 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 126 backendParam.allIssueParams.map{ issueParams => 127 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 128 setIQ.add(issueParams) 129 } 130 } 131 } 132 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 133 1 + setIQ.size / copyDistance 134 } 135 def rdPregIdxWidth: Int = { 136 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 137 } 138 139 def wbPregIdxWidth: Int = { 140 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 141 } 142 143 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 144 val writeFpFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf) 145 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVecRf) 146 val writeV0FuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeV0Rf) 147 val writeVlFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVlRf) 148 149 /** 150 * Check if this exu has certain latency 151 */ 152 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 153 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 154 def fpLatencyCertain: Boolean = writeFpFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 155 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 156 def v0LatencyCertain: Boolean = writeV0FuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 157 def vlLatencyCertain: Boolean = writeVlFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 158 // only load use it 159 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 160 161 /** 162 * Get mapping from FuType to Latency value. 163 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 164 * 165 * @return Map[ [[BigInt]], Latency] 166 */ 167 def fuLatencyMap: Map[FuType.OHType, Int] = { 168 if (latencyCertain) 169 if(needOg2) fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 170 else if (hasUncertainLatencyVal) 171 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 172 else 173 Map() 174 } 175 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 176 if (latencyCertain) 177 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 178 else if (hasUncertainLatencyVal) 179 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 180 else 181 Map() 182 } 183 184 /** 185 * Get set of latency of function units. 186 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 187 * 188 * @return Set[Latency] 189 */ 190 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 191 192 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 193 194 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 195 196 def intFuLatencyMap: Map[FuType.OHType, Int] = { 197 if (intLatencyCertain) { 198 if (isVfExeUnit) { 199 // vf exe unit writing back to int regfile should delay 1 cycle 200 // vf exe unit need og2 --> delay 1 cycle 201 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 2)).toMap 202 } else { 203 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 204 } 205 } 206 else 207 Map() 208 } 209 210 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 211 212 def fpFuLatencyMap: Map[FuType.OHType, Int] = { 213 if (fpLatencyCertain) 214 if (needOg2) writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 215 else 216 Map() 217 } 218 219 def fpLatencyValMax: Int = fpFuLatencyMap.values.fold(0)(_ max _) 220 221 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 222 if (vfLatencyCertain) 223 if(needOg2) writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 224 else 225 Map() 226 } 227 228 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 229 230 def v0FuLatencyMap: Map[FuType.OHType, Int] = { 231 if (v0LatencyCertain) 232 if(needOg2) writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 233 else 234 Map() 235 } 236 237 def v0LatencyValMax: Int = v0FuLatencyMap.values.fold(0)(_ max _) 238 239 def vlFuLatencyMap: Map[FuType.OHType, Int] = { 240 if (vlLatencyCertain) 241 if(needOg2) writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 242 else 243 Map() 244 } 245 246 def vlLatencyValMax: Int = vlFuLatencyMap.values.fold(0)(_ max _) 247 248 /** 249 * Check if this exu has fixed latency 250 */ 251 def isFixedLatency: Boolean = { 252 if (latencyCertain) 253 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 254 false 255 } 256 257 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 258 259 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 260 261 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 262 263 def hasAluFu = fuConfigs.map(_.fuType == FuType.alu).reduce(_ || _) 264 265 def hasi2vFu = fuConfigs.map(_.fuType == FuType.i2v).reduce(_ || _) 266 267 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 268 269 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 270 271 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 272 273 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 274 275 def hasVecLsFu = fuConfigs.map(x => FuType.FuTypeOrR(x.fuType, Seq(FuType.vldu, FuType.vstu))).reduce(_ || _) 276 277 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 278 279 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 280 281 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 282 283 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 284 285 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 286 287 def hasLoadExu = hasLoadFu || hasHyldaFu 288 289 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 290 291 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 292 293 def CanCompress = !hasBrhFu || (hasBrhFu && hasi2vFu) 294 295 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 296 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 297 } 298 299 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 300 301 def getWBSource: SchedulerType = { 302 schdType 303 } 304 305 def hasCrossWb: Boolean = { 306 schdType match { 307 case IntScheduler() => writeFpRf || writeVecRf 308 case VfScheduler() => writeIntRf 309 case _ => false 310 } 311 } 312 313 def canAccept(fuType: UInt): Bool = { 314 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 315 } 316 317 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 318 319 def bindBackendParam(param: BackendParams): Unit = { 320 backendParam = param 321 } 322 323 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 324 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 325 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 326 if (this.isIQWakeUpSource) { 327 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 328 } 329 val loadWakeUpSourcePairs = cfgs.filter(x => x.source.getExuParam(backendParam.allExuParams).hasLoadFu || x.source.getExuParam(backendParam.allExuParams).hasHyldaFu) 330 val wakeUpByLoadNames = loadWakeUpSourcePairs.map(_.sink.name).toSet 331 val thisWakeUpByNames = iqWakeUpSinkPairs.map(_.source.name).toSet 332 this.needLoadDependency = !(wakeUpByLoadNames & thisWakeUpByNames).isEmpty 333 println(s"${this.name}: needLoadDependency is ${this.needLoadDependency}") 334 } 335 336 def updateExuIdx(idx: Int): Unit = { 337 this.exuIdx = idx 338 } 339 340 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 341 342 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 343 344 def numWakeupFromIQ = this.iqWakeUpSinkPairs.size 345 346 def getIntWBPort = { 347 wbPortConfigs.collectFirst { 348 case x: IntWB => x 349 } 350 } 351 352 def getFpWBPort = { 353 wbPortConfigs.collectFirst { 354 case x: FpWB => x 355 } 356 } 357 358 def getVfWBPort = { 359 wbPortConfigs.collectFirst { 360 case x: VfWB => x 361 } 362 } 363 364 def getV0WBPort = { 365 wbPortConfigs.collectFirst { 366 case x: V0WB => x 367 } 368 } 369 370 def getVlWBPort = { 371 wbPortConfigs.collectFirst { 372 case x: VlWB => x 373 } 374 } 375 376 /** 377 * Get the [[DataConfig]] that this exu need to read 378 */ 379 def pregRdDataCfgSet: Set[DataConfig] = { 380 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 381 } 382 383 /** 384 * Get the [[DataConfig]] that this exu need to write 385 */ 386 def pregWbDataCfgSet: Set[DataConfig] = { 387 this.wbPortConfigs.map(_.dataCfg).toSet 388 } 389 390 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 391 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 392 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 393 394 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 395 396 exuSrcsCfgSet 397 } 398 399 /** 400 * Get the [[DataConfig]] mapped indices of source data of exu 401 * 402 * @example 403 * {{{ 404 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), V0Data(), VlData()) 405 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 406 * getRfReadSrcIdx(V0Data()) = Seq(3) 407 * getRfReadSrcIdx(VlData()) = Seq(4) 408 * }}} 409 * @return Map[DataConfig -> Seq[indices]] 410 */ 411 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 412 val dataCfgs = DataConfig.RegSrcDataSet 413 val rfRdDataCfgSet = this.getRfReadDataCfgSet 414 dataCfgs.toSeq.map { cfg => 415 ( 416 cfg, 417 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 418 if (set.contains(cfg)) 419 Option(srcIdx) 420 else 421 None 422 }.filter(_.nonEmpty).map(_.get) 423 ) 424 }.toMap 425 } 426 427 def genExuModule(implicit p: Parameters): ExeUnit = { 428 new ExeUnit(this) 429 } 430 431 def genExuInputBundle(implicit p: Parameters): ExuInput = { 432 new ExuInput(this) 433 } 434 435 def genExuInputCopySrcBundle(implicit p: Parameters): ExuInput = { 436 new ExuInput(this, hasCopySrc = true) 437 } 438 439 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 440 new ExuOutput(this) 441 } 442 443 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 444 new ExuBypassBundle(this) 445 } 446} 447