1package xiangshan.backend.exu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.HasXSParameter 7import xiangshan.backend.Bundles.{ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WakeUpConfig 11import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB, WbConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler} 14 15case class ExeUnitParams( 16 name : String, 17 fuConfigs : Seq[FuConfig], 18 wbPortConfigs : Seq[WbConfig], 19 rfrPortConfigs: Seq[Seq[RdConfig]], 20)( 21 implicit 22 val schdType: SchedulerType, 23) { 24 // calculated configs 25 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 26 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 27 28 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 29 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 30 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 31 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 32 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 33 val numSrc: Int = fuConfigs.map(_.numSrc).max 34 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 35 val readIntRf: Boolean = numIntSrc > 0 36 val readFpRf: Boolean = numFpSrc > 0 37 val readVecRf: Boolean = numVecSrc > 0 38 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 39 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 40 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 41 val writeVfRf: Boolean = writeFpRf || writeVecRf 42 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 43 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 44 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ || _) 45 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 46 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 47 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 48 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 49 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 50 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 51 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 52 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 53 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 54 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 55 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 56 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 57 val wbPregIdxWidth = if (wbPortConfigs.nonEmpty) wbPortConfigs.map(_.pregIdxWidth).max else 0 58 59 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 60 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 61 62 val latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_&&_) 63 val intLatencyCertain = if (writeIntFuConfigs.nonEmpty) writeIntFuConfigs.map(x => x.latency.latencyVal.nonEmpty).fold(true)(_ && _) else false 64 val vfLatencyCertain = if (writeVfFuConfigs.nonEmpty) writeVfFuConfigs.map(x => x.latency.latencyVal.nonEmpty).fold(true)(_ && _) else false 65 66 val fuLatencyMap: Option[Seq[(Int, Int)]] = if (latencyCertain) Some(fuConfigs.map(y => (y.fuType, y.latency.latencyVal.get))) else None 67 val latencyValMax: Option[Int] = fuLatencyMap.map(x => x.map(_._2).max) 68 69 val intFuLatencyMap = if (intLatencyCertain) Some(writeIntFuConfigs.map(y => (y.fuType, y.latency.latencyVal.get))) else None 70 val intLatencyValMax = intFuLatencyMap.map(x => x.map(_._2).max) 71 72 val vfFuLatencyMap = if (vfLatencyCertain) Some(writeVfFuConfigs.map(y => (y.fuType, y.latency.latencyVal.get))) else None 73 val vfLatencyValMax = vfFuLatencyMap.map(x => x.map(_._2).max) 74 75 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 76 77 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 78 79 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 80 81 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 82 83 def hasLoadFu = fuConfigs.map(_.fuType == FuType.ldu).reduce(_ || _) 84 85 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 86 87 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 88 89 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 90 91 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu 92 93 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 94 95 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 96 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 97 } 98 99 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 100 101 def getWBSource: SchedulerType = { 102 schdType 103 } 104 105 def hasCrossWb: Boolean = { 106 schdType match { 107 case IntScheduler() => writeFpRf || writeVecRf 108 case VfScheduler() => writeIntRf 109 case _ => false 110 } 111 } 112 113 def canAccept(fuType: UInt): Bool = { 114 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 115 } 116 117 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 118 119 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 120 this.iqWakeUpSourcePairs = cfgs.filter(_.source == this.name) 121 this.iqWakeUpSinkPairs = cfgs.filter(_.sink == this.name) 122 require(this.isIQWakeUpSource && !this.hasUncertainLatency) 123 } 124 125 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 126 127 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 128 129 def getIntWBPort = { 130 wbPortConfigs.collectFirst { 131 case x: IntWB => x 132 } 133 } 134 135 def getVfWBPort = { 136 wbPortConfigs.collectFirst { 137 case x: VfWB => x 138 } 139 } 140 141 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 142 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 143 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 144 145 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 146 147 exuSrcsCfgSet 148 } 149 150 def genExuModule(implicit p: Parameters): ExeUnit = { 151 new ExeUnit(this) 152 } 153 154 def genExuInputBundle(implicit p: Parameters): ExuInput = { 155 new ExuInput(this) 156 } 157 158 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 159 new ExuOutput(this) 160 } 161} 162