1package xiangshan.backend.exu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler} 14 15case class ExeUnitParams( 16 name : String, 17 fuConfigs : Seq[FuConfig], 18 wbPortConfigs : Seq[PregWB], 19 rfrPortConfigs: Seq[Seq[RdConfig]], 20)( 21 implicit 22 val schdType: SchedulerType, 23) { 24 // calculated configs 25 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 26 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 27 // used in bypass to select data of exu output 28 var exuIdx: Int = -1 29 var backendParam: BackendParams = null 30 31 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 32 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 33 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 34 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 35 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 36 val numSrc: Int = fuConfigs.map(_.numSrc).max 37 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 38 val readIntRf: Boolean = numIntSrc > 0 39 val readFpRf: Boolean = numFpSrc > 0 40 val readVecRf: Boolean = numVecSrc > 0 41 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 42 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 43 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 44 val writeVfRf: Boolean = writeFpRf || writeVecRf 45 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 46 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 47 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ || _) 48 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 49 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 50 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 51 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 52 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 53 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 54 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 55 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 56 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 57 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 58 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 59 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 60 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 61 62 def rdPregIdxWidth: Int = { 63 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 64 } 65 66 def wbPregIdxWidth: Int = { 67 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 68 } 69 70 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 71 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 72 73 /** 74 * Check if this exu has certain latency 75 */ 76 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 77 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 78 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 79 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ && _) 80 81 /** 82 * Get mapping from FuType to Latency value. 83 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 84 * 85 * @return Map[FuType, Latency] 86 */ 87 def fuLatencyMap: Map[Int, Int] = { 88 if (latencyCertain) 89 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 90 else if (hasUncertainLatencyVal) 91 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 92 else 93 Map() 94 } 95 96 /** 97 * Get set of latency of function units. 98 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 99 * 100 * @return Set[Latency] 101 */ 102 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 103 104 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 105 106 def intFuLatencyMap: Map[Int, Int] = { 107 if (intLatencyCertain) 108 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 109 else 110 Map() 111 } 112 113 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 114 115 def vfFuLatencyMap: Map[Int, Int] = { 116 if (vfLatencyCertain) 117 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 118 else 119 Map() 120 } 121 122 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 123 124 /** 125 * Check if this exu has fixed latency 126 */ 127 def isFixedLatency: Boolean = { 128 if (latencyCertain) 129 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 130 false 131 } 132 133 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 134 135 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 136 137 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 138 139 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 140 141 def hasLoadFu = fuConfigs.map(_.fuType == FuType.ldu).reduce(_ || _) 142 143 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 144 145 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 146 147 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 148 149 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu 150 151 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 152 153 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 154 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 155 } 156 157 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 158 159 def getWBSource: SchedulerType = { 160 schdType 161 } 162 163 def hasCrossWb: Boolean = { 164 schdType match { 165 case IntScheduler() => writeFpRf || writeVecRf 166 case VfScheduler() => writeIntRf 167 case _ => false 168 } 169 } 170 171 def canAccept(fuType: UInt): Bool = { 172 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 173 } 174 175 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 176 177 def bindBackendParam(param: BackendParams): Unit = { 178 backendParam = param 179 } 180 181 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 182 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 183 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 184 if (this.isIQWakeUpSource) 185 require(!this.hasUncertainLatency || hasLoadFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 186 } 187 188 def updateExuIdx(idx: Int): Unit = { 189 this.exuIdx = idx 190 } 191 192 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 193 194 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 195 196 def getIntWBPort = { 197 wbPortConfigs.collectFirst { 198 case x: IntWB => x 199 } 200 } 201 202 def getVfWBPort = { 203 wbPortConfigs.collectFirst { 204 case x: VfWB => x 205 } 206 } 207 208 /** 209 * Get the [[DataConfig]] that this exu need to read 210 */ 211 def pregRdDataCfgSet: Set[DataConfig] = { 212 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 213 } 214 215 /** 216 * Get the [[DataConfig]] that this exu need to write 217 */ 218 def pregWbDataCfgSet: Set[DataConfig] = { 219 this.wbPortConfigs.map(_.dataCfg).toSet 220 } 221 222 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 223 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 224 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 225 226 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 227 228 exuSrcsCfgSet 229 } 230 231 /** 232 * Get the [[DataConfig]] mapped indices of source data of exu 233 * 234 * @example 235 * {{{ 236 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 237 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 238 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 239 * getRfReadSrcIdx(VConfigData()) = Seq(4) 240 * }}} 241 * @return Map[DataConfig -> Seq[indices]] 242 */ 243 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 244 val dataCfgs = DataConfig.RegSrcDataSet 245 val rfRdDataCfgSet = this.getRfReadDataCfgSet 246 dataCfgs.toSeq.map { cfg => 247 ( 248 cfg, 249 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 250 if (set.contains(cfg)) 251 Option(srcIdx) 252 else 253 None 254 }.filter(_.nonEmpty).map(_.get) 255 ) 256 }.toMap 257 } 258 259 def genExuModule(implicit p: Parameters): ExeUnit = { 260 new ExeUnit(this) 261 } 262 263 def genExuInputBundle(implicit p: Parameters): ExuInput = { 264 new ExuInput(this) 265 } 266 267 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 268 new ExuOutput(this) 269 } 270 271 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 272 new ExuBypassBundle(this) 273 } 274} 275