1package xiangshan.backend.exu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.Bundles.{ExuInput, ExuOutput} 7import xiangshan.backend.datapath.DataConfig.DataConfig 8import xiangshan.backend.datapath.RdConfig._ 9import xiangshan.backend.datapath.WbConfig.{FpWB, IntWB, WbConfig} 10import xiangshan.backend.fu.{FuConfig, FuType} 11import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler} 12 13case class ExeUnitParams( 14 fuConfigs : Seq[FuConfig], 15 wbPortConfigs : Seq[WbConfig], 16 rfrPortConfigs: Seq[Seq[RdConfig]], 17)( 18 implicit 19 val schdType: SchedulerType, 20) { 21 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 22 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 23 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 24 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 25 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 26 val numSrc: Int = fuConfigs.map(_.numSrc).max 27 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 28 val readIntRf: Boolean = numIntSrc > 0 29 val readFpRf: Boolean = numFpSrc > 0 30 val readVecRf: Boolean = numVecSrc > 0 31 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 32 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 33 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 34 val writeVfRf: Boolean = writeFpRf || writeVecRf 35 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 36 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ || _) 37 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 38 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 39 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 40 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 41 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 42 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 43 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 44 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 45 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 46 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 47 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 48 val wbPregIdxWidth = if (wbPortConfigs.nonEmpty) wbPortConfigs.map(_.pregIdxWidth).max else 0 49 50 protected val latencyCertain = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_&&_) 51 val fuLatencyMap = if (latencyCertain) Some(fuConfigs.map(y => (y.fuType, y.latency.latencyVal.get))) else None 52 val latencyValMax = fuLatencyMap.map(x => x.map(_._2).max) 53 54 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 55 56 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 57 58 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 59 60 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 61 62 def hasLoadFu = fuConfigs.map(_.fuType == FuType.ldu).reduce(_ || _) 63 64 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 65 66 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 67 68 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu 69 70 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 71 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 72 } 73 74 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 75 76 def getWBSource: SchedulerType = { 77 schdType 78 } 79 80 def hasCrossWb: Boolean = { 81 schdType match { 82 case IntScheduler() => writeFpRf || writeVecRf 83 case VfScheduler() => writeIntRf 84 case _ => false 85 } 86 } 87 88 def canAccept(fuType: UInt): Bool = { 89 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 90 } 91 92 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 93 94 def getIntWBPort = { 95 wbPortConfigs.collectFirst { 96 case x: IntWB => x 97 } 98 } 99 100 def getFpWBPort = { 101 wbPortConfigs.collectFirst { 102 case x: FpWB => x 103 } 104 } 105 106 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 107 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 108 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 109 110 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 111 112 exuSrcsCfgSet 113 } 114 115 def genExuModule(implicit p: Parameters): ExeUnit = { 116 new ExeUnit(this) 117 } 118 119 def genExuInputBundle(implicit p: Parameters): ExuInput = { 120 new ExuInput(this) 121 } 122 123 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 124 new ExuOutput(this) 125 } 126} 127