1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, SchedulerType, VfScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 40 val numSrc: Int = fuConfigs.map(_.numSrc).max 41 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 42 val readIntRf: Boolean = numIntSrc > 0 43 val readFpRf: Boolean = numFpSrc > 0 44 val readVecRf: Boolean = numVecSrc > 0 45 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 46 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 47 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 48 val writeVfRf: Boolean = writeFpRf || writeVecRf 49 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 50 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 51 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ || _) 52 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 53 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 54 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 55 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 56 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 57 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 58 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 59 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 60 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 61 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 62 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 63 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 64 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 65 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 66 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 67 68 def copyNum: Int = { 69 val setIQ = mutable.Set[IssueBlockParams]() 70 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 71 backendParam.allIssueParams.map{ issueParams => 72 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 73 setIQ.add(issueParams) 74 } 75 } 76 } 77 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 78 1 + setIQ.size / copyDistance 79 } 80 def rdPregIdxWidth: Int = { 81 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 82 } 83 84 def wbPregIdxWidth: Int = { 85 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 86 } 87 88 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 89 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 90 91 /** 92 * Check if this exu has certain latency 93 */ 94 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 95 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 96 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 97 // only load use it 98 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 99 100 /** 101 * Get mapping from FuType to Latency value. 102 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 103 * 104 * @return Map[ [[BigInt]], Latency] 105 */ 106 def fuLatencyMap: Map[FuType.OHType, Int] = { 107 if (latencyCertain) 108 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 109 else if (hasUncertainLatencyVal) 110 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 111 else 112 Map() 113 } 114 115 /** 116 * Get set of latency of function units. 117 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 118 * 119 * @return Set[Latency] 120 */ 121 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 122 123 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 124 125 def intFuLatencyMap: Map[FuType.OHType, Int] = { 126 if (intLatencyCertain) 127 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 128 else 129 Map() 130 } 131 132 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 133 134 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 135 if (vfLatencyCertain) 136 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 137 else 138 Map() 139 } 140 141 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 142 143 /** 144 * Check if this exu has fixed latency 145 */ 146 def isFixedLatency: Boolean = { 147 if (latencyCertain) 148 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 149 false 150 } 151 152 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 153 154 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 155 156 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 157 158 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 159 160 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 161 162 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 163 164 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 165 166 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 167 168 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 169 170 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 171 172 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 173 174 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 175 176 def hasLoadExu = hasLoadFu || hasHyldaFu 177 178 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 179 180 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 181 182 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 183 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 184 } 185 186 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 187 188 def getWBSource: SchedulerType = { 189 schdType 190 } 191 192 def hasCrossWb: Boolean = { 193 schdType match { 194 case IntScheduler() => writeFpRf || writeVecRf 195 case VfScheduler() => writeIntRf 196 case _ => false 197 } 198 } 199 200 def canAccept(fuType: UInt): Bool = { 201 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 202 } 203 204 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 205 206 def bindBackendParam(param: BackendParams): Unit = { 207 backendParam = param 208 } 209 210 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 211 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 212 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 213 if (this.isIQWakeUpSource) { 214 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 215 } 216 } 217 218 def updateExuIdx(idx: Int): Unit = { 219 this.exuIdx = idx 220 } 221 222 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 223 224 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 225 226 def getIntWBPort = { 227 wbPortConfigs.collectFirst { 228 case x: IntWB => x 229 } 230 } 231 232 def getVfWBPort = { 233 wbPortConfigs.collectFirst { 234 case x: VfWB => x 235 } 236 } 237 238 /** 239 * Get the [[DataConfig]] that this exu need to read 240 */ 241 def pregRdDataCfgSet: Set[DataConfig] = { 242 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 243 } 244 245 /** 246 * Get the [[DataConfig]] that this exu need to write 247 */ 248 def pregWbDataCfgSet: Set[DataConfig] = { 249 this.wbPortConfigs.map(_.dataCfg).toSet 250 } 251 252 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 253 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 254 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 255 256 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 257 258 exuSrcsCfgSet 259 } 260 261 /** 262 * Get the [[DataConfig]] mapped indices of source data of exu 263 * 264 * @example 265 * {{{ 266 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 267 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 268 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 269 * getRfReadSrcIdx(VConfigData()) = Seq(4) 270 * }}} 271 * @return Map[DataConfig -> Seq[indices]] 272 */ 273 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 274 val dataCfgs = DataConfig.RegSrcDataSet 275 val rfRdDataCfgSet = this.getRfReadDataCfgSet 276 dataCfgs.toSeq.map { cfg => 277 ( 278 cfg, 279 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 280 if (set.contains(cfg)) 281 Option(srcIdx) 282 else 283 None 284 }.filter(_.nonEmpty).map(_.get) 285 ) 286 }.toMap 287 } 288 289 def genExuModule(implicit p: Parameters): ExeUnit = { 290 new ExeUnit(this) 291 } 292 293 def genExuInputBundle(implicit p: Parameters): ExuInput = { 294 new ExuInput(this) 295 } 296 297 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 298 new ExuOutput(this) 299 } 300 301 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 302 new ExuBypassBundle(this) 303 } 304} 305