xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala (revision 8882eb685de93177da606ee717b5ec8e459a768a) 
1package xiangshan.backend.fu.NewCSR.CSREvents
2
3import chisel3._
4import chisel3.util._
5import org.chipsalliance.cde.config.Parameters
6import utility.{SignExt, ZeroExt}
7import xiangshan.HasXSParameter
8import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, PrivState}
9import xiangshan.backend.fu.NewCSR.CSRConfig._
10import xiangshan.backend.fu.NewCSR.CSRDefines.{HgatpMode, SatpMode}
11import xiangshan.backend.fu.NewCSR._
12
13trait CSREvents { self: NewCSR =>
14  val trapEntryDEvent = Module(new TrapEntryDEventModule)
15
16  val trapEntryMEvent = Module(new TrapEntryMEventModule)
17
18  val trapEntryMNEvent = Module(new TrapEntryMNEventModule())
19
20  val trapEntryHSEvent = Module(new TrapEntryHSEventModule)
21
22  val trapEntryVSEvent = Module(new TrapEntryVSEventModule)
23
24  val mretEvent  = Module(new MretEventModule)
25
26  val mnretEvent = Module(new MNretEventModule)
27
28  val sretEvent  = Module(new SretEventModule)
29
30  val dretEvent  = Module(new DretEventModule)
31
32  val events: Seq[Module with CSREventBase] = Seq(
33    trapEntryDEvent,
34    trapEntryMEvent,
35    trapEntryHSEvent,
36    trapEntryVSEvent,
37    trapEntryMNEvent,
38    mretEvent,
39    sretEvent,
40    dretEvent,
41    mnretEvent,
42  )
43
44  events.foreach(x => dontTouch(x.out))
45
46  val trapEntryEvents: Seq[Module with CSREventBase] = Seq(
47    trapEntryDEvent,
48    trapEntryMEvent,
49    trapEntryHSEvent,
50    trapEntryVSEvent,
51  )
52}
53
54trait EventUpdatePrivStateOutput {
55  val privState = ValidIO(new PrivState)
56}
57
58trait EventOutputBase {
59  import scala.reflect.runtime.{universe => ru}
60
61  def getBundleByName(name: String): Valid[CSRBundle] = {
62    val mirror: ru.Mirror = ru.runtimeMirror(getClass.getClassLoader)
63    val im = mirror.reflect(this)
64    val classSymbol: ru.ClassSymbol = im.symbol.asClass
65    val fieldSymbol = classSymbol.info.decl(ru.TermName(name)).asTerm
66    val fieldMirror: ru.FieldMirror = mirror.reflect(this).reflectField(fieldSymbol)
67    fieldMirror.get.asInstanceOf[Valid[CSRBundle]]
68  }
69}
70
71trait CSREventBase {
72  val valid = IO(Input(Bool()))
73  val in: Bundle
74  val out: Bundle
75
76  def genTrapVA(
77    transMode: PrivState,
78    satp: SatpBundle,
79    vsatp: SatpBundle,
80    hgatp: HgatpBundle,
81    addr: UInt,
82  ) = {
83    require(addr.getWidth >= 50)
84
85    val isBare =
86      transMode.isModeM ||
87      transMode.isModeHSorHU &&  satp.MODE === SatpMode.Bare ||
88      transMode.isVirtual    && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Bare
89    val isSv39 =
90      transMode.isModeHSorHU &&  satp.MODE === SatpMode.Sv39 ||
91      transMode.isVirtual    && vsatp.MODE === SatpMode.Sv39
92    val isSv48 =
93      transMode.isModeHSorHU &&  satp.MODE === SatpMode.Sv48 ||
94      transMode.isVirtual    && vsatp.MODE === SatpMode.Sv48
95    val isSv39x4 =
96      transMode.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv39x4
97    val isSv48x4 =
98      transMode.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv48x4
99
100    val bareAddr   = ZeroExt(addr(PAddrWidth - 1, 0), XLEN)
101    // When enable virtual memory, the higher bit should fill with the msb of address of Sv39/Sv48/Sv57
102    val sv39Addr   = SignExt(addr.take(39), XLEN)
103    val sv39x4Addr = ZeroExt(addr.take(39 + 2), XLEN)
104    val sv48Addr   = SignExt(addr.take(48), XLEN)
105    val sv48x4Addr = ZeroExt(addr.take(48 + 2), XLEN)
106
107    val trapAddr = Mux1H(Seq(
108      isBare   -> bareAddr,
109      isSv39   -> sv39Addr,
110      isSv39x4 -> sv39x4Addr,
111      isSv48   -> sv48Addr,
112      isSv48x4 -> sv48x4Addr,
113    ))
114
115    trapAddr
116  }
117}
118
119class TrapEntryEventInput(implicit val p: Parameters) extends Bundle with HasXSParameter {
120  val causeNO = Input(new CauseBundle)
121  val trapPc = Input(UInt(VaddrMaxWidth.W))
122  val trapPcGPA = Input(UInt(PAddrBitsMax.W))
123  val trapInst = Input(ValidIO(UInt(InstWidth.W)))
124  val fetchMalTval = Input(UInt(XLEN.W))
125  val isCrossPageIPF = Input(Bool())
126  val isHls = Input(Bool())
127  val isFetchMalAddr = Input(Bool())
128  val isFetchBkpt = Input(Bool())
129  val trapIsForVSnonLeafPTE = Input(Bool())
130  val hasDTExcp = Input(Bool())
131
132  // always current privilege
133  val iMode = Input(new PrivState())
134  // take MRPV into consideration
135  val dMode = Input(new PrivState())
136  // status
137  val privState = Input(new PrivState)
138  val mstatus = Input(new MstatusBundle)
139  val hstatus = Input(new HstatusBundle)
140  val sstatus = Input(new SstatusBundle)
141  val vsstatus = Input(new SstatusBundle)
142  // envcfg
143  val menvcfg = Input(new MEnvCfg)
144  val henvcfg = Input(new HEnvCfg)
145
146  val pcFromXtvec = Input(UInt(XLEN.W))
147
148  val satp = Input(new SatpBundle)
149  val vsatp = Input(new SatpBundle)
150  val hgatp = Input(new HgatpBundle)
151  val mbmc = Input(new MbmcBundle)
152  // from mem
153  val memExceptionVAddr = Input(UInt(XLEN.W))
154  val memExceptionGPAddr = Input(UInt(XLEN.W))
155  val memExceptionIsForVSnonLeafPTE = Input(Bool())
156  val virtualInterruptIsHvictlInject = Input(Bool())
157  val hvictlIID = Input(UInt(HIIDWidth.W))
158}
159
160trait EventSinkBundle { self: CSRModule[_ <: CSRBundle] =>
161  protected def addUpdateBundleInCSREnumType(updateBundle: ValidIO[CSRBundle]): Unit = {
162    (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case (sink, source) =>
163      if (updateBundle.bits.eventFields.contains(source)) {
164        sink.addOtherUpdate(updateBundle.valid, source)
165      }
166    }
167  }
168}
169
170class TargetPCBundle extends Bundle {
171  val pc = UInt(XLEN.W)
172  val raiseIPF = Bool()
173  val raiseIAF = Bool()
174  val raiseIGPF = Bool()
175
176  def raiseFault = raiseIPF || raiseIAF || raiseIGPF
177}
178