1package xiangshan.backend.fu.NewCSR.CSREvents 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import xiangshan.backend.fu.NewCSR.CSRConfig.VaddrMaxWidth 7import xiangshan.backend.fu.NewCSR.CSRDefines.{HgatpMode, PrivMode, SatpMode, VirtMode} 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.AddrTransType 10 11 12class DretEventOutput extends Bundle with EventUpdatePrivStateOutput with EventOutputBase { 13 val dcsr = ValidIO((new DcsrBundle).addInEvent(_.V, _.PRV)) 14 val mstatus = ValidIO((new MstatusBundle).addInEvent(_.MPRV, _.MDT, _.SDT)) 15 val vsstatus = ValidIO((new SstatusBundle).addInEvent(_.SDT)) 16 val debugMode = ValidIO(Bool()) 17 val debugIntrEnable = ValidIO(Bool()) 18 val targetPc = ValidIO(new TargetPCBundle) 19} 20 21class DretEventInput extends Bundle { 22 val dcsr = Input(new DcsrBundle) 23 val dpc = Input(new Epc) 24 val mstatus = Input(new MstatusBundle) 25 val vsstatus = Input(new SstatusBundle) 26 val satp = Input(new SatpBundle) 27 val vsatp = Input(new SatpBundle) 28 val hgatp = Input(new HgatpBundle) 29} 30 31class DretEventModule(implicit p: Parameters) extends Module with CSREventBase { 32 val in = IO(new DretEventInput) 33 val out = IO(new DretEventOutput) 34 35 private val satp = in.satp 36 private val vsatp = in.vsatp 37 private val hgatp = in.hgatp 38 private val nextPrivState = out.privState.bits 39 40 private val instrAddrTransType = AddrTransType( 41 bare = nextPrivState.isModeM || 42 (!nextPrivState.isVirtual && satp.MODE === SatpMode.Bare) || 43 (nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Bare), 44 sv39 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv39 || 45 nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv39, 46 sv48 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv48 || 47 nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv48, 48 sv39x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv39x4, 49 sv48x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv48x4 50 ) 51 52 out := DontCare 53 54 out.debugMode.valid := valid 55 out.privState.valid := valid 56 out.dcsr.valid := valid 57 out.mstatus.valid := valid 58 out.vsstatus.valid := valid 59 out.debugIntrEnable.valid := valid 60 out.targetPc.valid := valid 61 62 out.privState.bits.PRVM := in.dcsr.PRV.asUInt 63 out.privState.bits.V := Mux(in.dcsr.PRV === PrivMode.M, VirtMode.Off.asUInt, in.dcsr.V.asUInt) 64 out.mstatus.bits.MPRV := Mux(!out.privState.bits.isModeM, 0.U, in.mstatus.MPRV.asUInt) 65 out.mstatus.bits.MDT := Mux(!out.privState.bits.isModeM, 0.U, in.mstatus.MDT.asBool) 66 out.mstatus.bits.SDT := Mux(out.privState.bits.isVirtual || out.privState.bits.isModeHU, 0.U, in.mstatus.SDT.asBool) 67 out.vsstatus.bits.SDT := Mux(out.privState.bits.isModeVU, 0.U, in.vsstatus.SDT.asBool) 68 out.debugMode.bits := false.B 69 out.debugIntrEnable.bits := true.B 70 out.targetPc.bits.pc := in.dpc.asUInt 71 out.targetPc.bits.raiseIPF := instrAddrTransType.checkPageFault(in.dpc.asUInt) 72 out.targetPc.bits.raiseIAF := instrAddrTransType.checkAccessFault(in.dpc.asUInt) 73 out.targetPc.bits.raiseIGPF := instrAddrTransType.checkGuestPageFault(in.dpc.asUInt) 74} 75 76trait DretEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] => 77 val retFromD = IO(Flipped(new DretEventOutput)) 78 79 addUpdateBundleInCSREnumType(retFromD.getBundleByName(self.modName.toLowerCase())) 80 81 reconnectReg() 82} 83