1package xiangshan.backend.fu.NewCSR.CSREvents 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility.{SignExt, ZeroExt} 7import xiangshan.ExceptionNO 8import xiangshan.ExceptionNO._ 9import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState} 10import xiangshan.backend.fu.NewCSR.CSRConfig.{VaddrMaxWidth, XLEN} 11import xiangshan.backend.fu.NewCSR.CSRDefines.{HgatpMode, PrivMode, SatpMode, VirtMode} 12import xiangshan.backend.fu.NewCSR._ 13import xiangshan.AddrTransType 14 15 16class MNretEventOutput extends Bundle with EventUpdatePrivStateOutput with EventOutputBase { 17 val mnstatus = ValidIO((new MnstatusBundle).addInEvent(_.MNPP, _.MNPV, _.NMIE)) 18 val mstatus = ValidIO((new MstatusBundle).addInEvent(_.MPRV, _.MDT, _.SDT)) 19 val vsstatus = ValidIO((new SstatusBundle).addInEvent(_.SDT)) 20 val targetPc = ValidIO(new TargetPCBundle) 21} 22 23class MNretEventInput extends Bundle { 24 val mnstatus = Input(new MnstatusBundle) 25 val mstatus = Input(new MstatusBundle) 26 val mnepc = Input(new Epc()) 27 val satp = Input(new SatpBundle) 28 val vsatp = Input(new SatpBundle) 29 val hgatp = Input(new HgatpBundle) 30 val vsstatus = Input(new SstatusBundle) 31} 32 33class MNretEventModule(implicit p: Parameters) extends Module with CSREventBase { 34 val in = IO(new MNretEventInput) 35 val out = IO(new MNretEventOutput) 36 37 private val satp = in.satp 38 private val vsatp = in.vsatp 39 private val hgatp = in.hgatp 40 private val nextPrivState = out.privState.bits 41 42 private val instrAddrTransType = AddrTransType( 43 bare = nextPrivState.isModeM || 44 (!nextPrivState.isVirtual && satp.MODE === SatpMode.Bare) || 45 (nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Bare), 46 sv39 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv39 || 47 nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv39, 48 sv48 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv48 || 49 nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv48, 50 sv39x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv39x4, 51 sv48x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv48x4 52 ) 53 54 val outPrivState = Wire(new PrivState) 55 outPrivState.PRVM := in.mnstatus.MNPP 56 outPrivState.V := Mux(in.mnstatus.MNPP === PrivMode.M, VirtMode.Off.asUInt, in.mnstatus.MNPV.asUInt) 57 58 val mnretToM = outPrivState.isModeM 59 val mnretToS = outPrivState.isModeHS 60 val mnretToVU = outPrivState.isModeVU 61 62 out := DontCare 63 64 out.privState.valid := valid 65 out.mnstatus .valid := valid 66 out.mstatus .valid := valid 67 out.vsstatus .valid := valid 68 out.targetPc .valid := valid 69 70 out.privState.bits := outPrivState 71 out.mnstatus.bits.MNPP := PrivMode.U 72 out.mnstatus.bits.MNPV := VirtMode.Off.asUInt 73 out.mnstatus.bits.NMIE := 1.U 74 out.mstatus.bits.MPRV := Mux(in.mnstatus.MNPP =/= PrivMode.M, 0.U, in.mstatus.MPRV.asUInt) 75 // clear MDT when mnret to below M 76 out.mstatus.bits.MDT := Mux(mnretToM, in.mstatus.MDT.asBool, 0.U) 77 out.mstatus.bits.SDT := Mux(mnretToM || mnretToS, in.mstatus.SDT.asBool, 0.U) 78 out.vsstatus.bits.SDT := Mux(mnretToVU, 0.U, in.vsstatus.SDT.asBool) 79 out.targetPc.bits.pc := in.mnepc.asUInt 80 out.targetPc.bits.raiseIPF := instrAddrTransType.checkPageFault(in.mnepc.asUInt) 81 out.targetPc.bits.raiseIAF := instrAddrTransType.checkAccessFault(in.mnepc.asUInt) 82 out.targetPc.bits.raiseIGPF := instrAddrTransType.checkGuestPageFault(in.mnepc.asUInt) 83} 84 85trait MNretEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] => 86 val retFromMN = IO(Flipped(new MNretEventOutput)) 87 88 addUpdateBundleInCSREnumType(retFromMN.getBundleByName(self.modName.toLowerCase())) 89 90 reconnectReg() 91}