1package xiangshan.backend.fu.NewCSR.CSREvents 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility.{SignExt, ZeroExt} 7import xiangshan.ExceptionNO 8import xiangshan.ExceptionNO._ 9import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState} 10import xiangshan.backend.fu.NewCSR.CSRConfig.{VaddrMaxWidth, XLEN} 11import xiangshan.backend.fu.NewCSR.CSRDefines.{HgatpMode, PrivMode, SatpMode, VirtMode} 12import xiangshan.backend.fu.NewCSR._ 13import xiangshan.AddrTransType 14 15 16class MretEventOutput extends Bundle with EventUpdatePrivStateOutput with EventOutputBase { 17 val mstatus = ValidIO((new MstatusBundle).addInEvent(_.MPP, _.MPV, _.MIE, _.MPIE, _.MPRV, _.MDT, _.SDT)) 18 val vsstatus = ValidIO((new SstatusBundle).addInEvent(_.SDT)) 19 val targetPc = ValidIO(new TargetPCBundle) 20} 21 22class MretEventInput extends Bundle { 23 val mstatus = Input(new MstatusBundle) 24 val vsstatus = Input(new SstatusBundle) 25 val mepc = Input(new Epc()) 26 val satp = Input(new SatpBundle) 27 val vsatp = Input(new SatpBundle) 28 val hgatp = Input(new HgatpBundle) 29} 30 31class MretEventModule(implicit p: Parameters) extends Module with CSREventBase { 32 val in = IO(new MretEventInput) 33 val out = IO(new MretEventOutput) 34 35 private val satp = in.satp 36 private val vsatp = in.vsatp 37 private val hgatp = in.hgatp 38 private val nextPrivState = out.privState.bits 39 40 private val instrAddrTransType = AddrTransType( 41 bare = nextPrivState.isModeM || 42 (!nextPrivState.isVirtual && satp.MODE === SatpMode.Bare) || 43 (nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Bare), 44 sv39 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv39 || 45 nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv39, 46 sv48 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv48 || 47 nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv48, 48 sv39x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv39x4, 49 sv48x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv48x4 50 ) 51 val outPrivState = Wire(new PrivState) 52 outPrivState.PRVM := in.mstatus.MPP 53 outPrivState.V := Mux(in.mstatus.MPP === PrivMode.M, VirtMode.Off.asUInt, in.mstatus.MPV.asUInt) 54 55 val mretToM = outPrivState.isModeM 56 val mretToS = outPrivState.isModeHS 57 val mretToVu = outPrivState.isModeVU 58 59 out := DontCare 60 61 out.privState.valid := valid 62 out.mstatus .valid := valid 63 out.targetPc .valid := valid 64 65 out.privState.bits := outPrivState 66 out.mstatus.bits.MPP := PrivMode.U 67 out.mstatus.bits.MPV := VirtMode.Off.asUInt 68 out.mstatus.bits.MIE := in.mstatus.MPIE 69 out.mstatus.bits.MPIE := 1.U 70 out.mstatus.bits.MPRV := Mux(in.mstatus.MPP =/= PrivMode.M, 0.U, in.mstatus.MPRV.asUInt) 71 // clear MDT when return mret always execute in M mode 72 out.mstatus.bits.MDT := 0.U 73 // clear sstatus.SDT when return mode below M and HS 74 out.mstatus.bits.SDT := Mux(mretToM || mretToS, in.mstatus.SDT.asBool, 0.U) 75 // clear vsstatus.SDT when return to VU 76 out.vsstatus.bits.SDT := Mux(mretToVu, 0.U, in.vsstatus.SDT.asBool) 77 78 out.targetPc.bits.pc := in.mepc.asUInt 79 out.targetPc.bits.raiseIPF := instrAddrTransType.checkPageFault(in.mepc.asUInt) 80 out.targetPc.bits.raiseIAF := instrAddrTransType.checkAccessFault(in.mepc.asUInt) 81 out.targetPc.bits.raiseIGPF := instrAddrTransType.checkGuestPageFault(in.mepc.asUInt) 82} 83 84trait MretEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] => 85 val retFromM = IO(Flipped(new MretEventOutput)) 86 87 addUpdateBundleInCSREnumType(retFromM.getBundleByName(self.modName.toLowerCase())) 88 89 reconnectReg() 90} 91