1package xiangshan.backend.fu.NewCSR.CSREvents 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility.{SignExt, ZeroExt} 7import xiangshan.{ExceptionNO, HasXSParameter, TriggerAction} 8import xiangshan.ExceptionNO._ 9import xiangshan.backend.fu.NewCSR 10import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState} 11import xiangshan.backend.fu.NewCSR.CSRConfig.{VaddrMaxWidth, XLEN} 12import xiangshan.backend.fu.NewCSR.CSRDefines.SatpMode 13import xiangshan.backend.fu.NewCSR._ 14 15 16class TrapEntryDEventOutput extends Bundle with EventUpdatePrivStateOutput with EventOutputBase { 17 val dcsr = ValidIO((new DcsrBundle).addInEvent(_.CAUSE, _.V, _.PRV)) 18 val dpc = ValidIO((new Epc ).addInEvent(_.epc)) 19 val targetPc = ValidIO(new TargetPCBundle) 20 val debugMode = ValidIO(Bool()) 21 val debugIntrEnable = ValidIO(Bool()) 22} 23 24class TrapEntryDEventInput(implicit override val p: Parameters) extends TrapEntryEventInput{ 25 val hasTrap = Input(Bool()) 26 val debugMode = Input(Bool()) 27 val hasDebugIntr = Input(Bool()) 28 val triggerEnterDebugMode = Input(Bool()) 29 val hasDebugEbreakException = Input(Bool()) 30 val hasSingleStep = Input(Bool()) 31 val breakPoint = Input(Bool()) 32 val criticalErrorStateEnterDebug = Input(Bool()) 33} 34 35class TrapEntryDEventModule(implicit val p: Parameters) extends Module with CSREventBase with DebugMMIO { 36 val in = IO(new TrapEntryDEventInput) 37 val out = IO(new TrapEntryDEventOutput) 38 39 private val current = in 40 private val iMode = current.iMode 41 private val satp = current.satp 42 private val vsatp = current.vsatp 43 private val hgatp = current.hgatp 44 45 private val hasTrap = in.hasTrap 46 private val debugMode = in.debugMode 47 private val hasDebugIntr = in.hasDebugIntr 48 private val breakPoint = in.breakPoint 49 private val triggerEnterDebugMode = in.triggerEnterDebugMode 50 private val hasDebugEbreakException = in.hasDebugEbreakException 51 private val hasSingleStep = in.hasSingleStep 52 private val criticalErrorStateEnterDebug = in.criticalErrorStateEnterDebug 53 54 private val hasExceptionInDmode = debugMode && hasTrap 55 val causeIntr = DcsrCause.Haltreq.asUInt 56 val causeExp = MuxCase(DcsrCause.None.asUInt, Seq( 57 criticalErrorStateEnterDebug -> DcsrCause.Other.asUInt, 58 triggerEnterDebugMode -> DcsrCause.Trigger.asUInt, 59 hasDebugEbreakException -> DcsrCause.Ebreak.asUInt, 60 hasSingleStep -> DcsrCause.Step.asUInt 61 )) 62 63 private val trapPC = genTrapVA( 64 iMode, 65 satp, 66 vsatp, 67 hgatp, 68 in.trapPc, 69 ) 70 71 // ebreak jump debugEntry not debugException in dmode 72 // debug rom make hart write 0 to DebugMMIO.EXCEPTION when exception happened in debugMode. 73 // let debug module known hart got an exception. 74 // note: Need't know exception number in debugMode. 75 // exception(EX_BP) must be ebreak here! 76 val debugPc = Mux(hasExceptionInDmode && !breakPoint, DebugException.U, DebugEntry.U) 77 78 out := DontCare 79 // output 80 out.dcsr.valid := valid 81 out.dpc.valid := valid 82 // !debugMode trap || debugMode hasExp 83 out.targetPc.valid := valid || hasExceptionInDmode 84 out.debugMode.valid := valid 85 out.privState.valid := valid 86 out.debugIntrEnable.valid := valid 87 88 out.dcsr.bits.V := current.privState.V.asUInt 89 out.dcsr.bits.PRV := current.privState.PRVM.asUInt 90 out.dcsr.bits.CAUSE := Mux(hasDebugIntr, causeIntr, causeExp) 91 out.dpc.bits.epc := trapPC(63, 1) 92 93 out.targetPc.bits.pc := debugPc 94 out.targetPc.bits.raiseIPF := false.B 95 out.targetPc.bits.raiseIAF := false.B 96 out.targetPc.bits.raiseIGPF := false.B 97 out.debugMode.bits := true.B 98 out.privState.bits := PrivState.ModeM 99 out.debugIntrEnable.bits := false.B 100 101} 102 103trait TrapEntryDEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] => 104 val trapToD = IO(Flipped(new TrapEntryDEventOutput)) 105 106 addUpdateBundleInCSREnumType(trapToD.getBundleByName(self.modName.toLowerCase())) 107 108 reconnectReg() 109} 110