1package xiangshan.backend.fu.NewCSR 2 3import chisel3._ 4import freechips.rocketchip.rocket.CSRs 5import org.chipsalliance.cde.config.Parameters 6import xiangshan.{DistributedCSRIO, XSModule} 7import xiangshan.backend.fu.NewCSR.CSRConfig._ 8 9class PFEvent(implicit p: Parameters) extends XSModule { 10 val io = IO(new Bundle { 11 val distribute_csr = Flipped(new DistributedCSRIO()) 12 val hpmevent = Output(Vec(perfCntNum, UInt(XLEN.W))) 13 }) 14 15 val w = io.distribute_csr.w 16 17 val perfEvents: Seq[CSRModule[_]] = (0 until perfCntNum).map(num => 18 Module(new CSRModule(s"perfEvents", new MhpmeventBundle)) 19 .setAddr(CSRs.mhpmevent3 + num) 20 ) 21 22 perfEvents.zip(io.hpmevent).map{case(perf, out) => { 23 perf.w.wen := w.valid && (w.bits.addr === perf.addr.U) 24 perf.w.wdata := w.bits.data 25 out := perf.rdata 26 }} 27}