xref: /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala (revision 9e200047e3e84d1588ae9ea8bd96d3eade2c7638) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.fu.fpu
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import xiangshan.backend.fu.{FuncUnit, HasPipelineReg}
23import xiangshan.backend.fu.FuConfig
24import xiangshan.{FPUCtrlSignals, XSModule}
25
26trait HasUIntToSIntHelper {
27  implicit class UIntToSIntHelper(x: UInt){
28    def toSInt: SInt = Cat(0.U(1.W), x).asSInt
29  }
30}
31
32abstract class FPUDataModule(implicit p: Parameters) extends XSModule {
33  val io = IO(new Bundle() {
34    val in = Input(new Bundle() {
35      val src = Vec(3, UInt(64.W))
36      val fpCtrl = new FPUCtrlSignals
37      val rm = UInt(3.W)
38    })
39    val out = Output(new Bundle() {
40      val data = UInt(64.W)
41      val fflags = UInt(5.W)
42    })
43  })
44
45  val rm = Mux(io.in.fpCtrl.rm === "b111".U, io.in.rm, io.in.fpCtrl.rm)
46}
47
48abstract class FPUSubModule(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
49  with HasUIntToSIntHelper
50{
51  val dataModule: FPUDataModule
52  def connectDataModule = {
53    for (i <- 0 until dataModule.io.in.src.length) {
54      dataModule.io.in.src(i) := (if (i < io.in.bits.data.src.length) io.in.bits.data.src(i) else 0.U)
55    }
56    io.in.bits.ctrl.fpu.foreach(_ <> dataModule.io.in.fpCtrl)
57    dataModule.io.in.rm <> io.frm.get
58    io.out.bits.res.data := dataModule.io.out.data
59    io.out.bits.res.fflags.get := dataModule.io.out.fflags
60  }
61  def invert_sign(x: UInt, len: Int) = {
62    Cat(
63      !x(len-1), x(len-2, 0)
64    )
65  }
66}
67
68abstract class FPUPipelineModule(cfg: FuConfig)(implicit p: Parameters)
69  extends FPUSubModule(cfg)
70  with HasPipelineReg
71{
72  override def latency: Int = cfg.latency.latencyVal.get
73}
74