xref: /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala (revision 367512b707c976b7ff3fa2e0a4cf1b35a5c1d3c2) 
1package xiangshan.backend.fu.fpu
2
3import chisel3._
4import chisel3.util._
5import xiangshan.backend.fu.{FuConfig, FunctionUnit, HasPipelineReg}
6
7trait HasUIntToSIntHelper {
8  implicit class UIntToSIntHelper(x: UInt){
9    def toSInt: SInt = Cat(0.U(1.W), x).asSInt()
10  }
11}
12
13abstract class FPUSubModule extends FunctionUnit(len = 65)
14  with HasUIntToSIntHelper
15{
16  val rm = IO(Input(UInt(3.W)))
17  val fflags = IO(Output(UInt(5.W)))
18}
19
20abstract class FPUPipelineModule
21  extends FPUSubModule
22  with HasPipelineReg