xref: /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala (revision 3b739f49c5a26805be859c7231717ecc38aade30) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.fu.fpu
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import utility.DataHoldBypass
23import xiangshan.v2backend.FuConfig
24import xiangshan.{FPUCtrlSignals, XSModule}
25import xiangshan.v2backend.fu.{FuncUnit, HasPipelineReg}
26
27trait HasUIntToSIntHelper {
28  implicit class UIntToSIntHelper(x: UInt){
29    def toSInt: SInt = Cat(0.U(1.W), x).asSInt()
30  }
31}
32
33abstract class FPUDataModule(implicit p: Parameters) extends XSModule {
34  val io = IO(new Bundle() {
35    val in = Input(new Bundle() {
36      val src = Vec(3, UInt(64.W))
37      val fpCtrl = new FPUCtrlSignals
38      val rm = UInt(3.W)
39    })
40    val out = Output(new Bundle() {
41      val data = UInt(64.W)
42      val fflags = UInt(5.W)
43    })
44  })
45
46  val rm = io.in.rm
47  val fflags = io.out.fflags
48}
49
50abstract class FPUSubModule(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
51  with HasUIntToSIntHelper
52{
53//  val rm = IO(Input(UInt(3.W)))
54  val fflags = IO(Output(UInt(5.W)))
55  val dataModule: FPUDataModule
56  def connectDataModule = {
57    for (i <- 0 until dataModule.io.in.src.length) {
58      dataModule.io.in.src(i) := (if (i < io.in.bits.src.length) io.in.bits.src(i) else 0.U)
59    }
60    io.in.bits.fpu.foreach(_ <> dataModule.io.in.fpCtrl)
61    dataModule.io.in.rm <> io.frm.get
62    io.out.bits.data := dataModule.io.out.data
63    fflags := dataModule.io.out.fflags
64    io.out.bits.fflags.get := fflags
65    io.out.bits.robIdx := RegEnable(io.in.bits.robIdx, io.in.fire)
66    io.out.bits.fpu.foreach(_ := io.in.bits.fpu.get)
67    io.out.bits.pdest := RegEnable(io.in.bits.pdest, io.in.fire)
68  }
69  def invert_sign(x: UInt, len: Int) = {
70    Cat(
71      !x(len-1), x(len-2, 0)
72    )
73  }
74}
75
76abstract class FPUPipelineModule(cfg: FuConfig)(implicit p: Parameters)
77  extends FPUSubModule(cfg)
78  with HasPipelineReg
79