1package xiangshan.backend.fu.fpu 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan.backend.fu.{FuConfig, FunctionUnit, HasPipelineReg} 6 7 8class FPUSubModuleInput extends Bundle{ 9 val op = UInt(3.W) 10 val isDouble = Bool() 11 val a, b, c = UInt(64.W) 12 val rm = UInt(3.W) 13} 14 15class FPUSubModuleOutput extends Bundle{ 16 val fflags = new Fflags 17 val result = UInt(64.W) 18} 19 20class FPUSubModuleIO extends Bundle{ 21 val in = Flipped(DecoupledIO(new FPUSubModuleInput)) 22 val out = DecoupledIO(new FPUSubModuleOutput) 23} 24 25//trait HasPipelineReg { this: FPUSubModule => 26// def latency: Int 27// 28// val ready = Wire(Bool()) 29// val cnt = RegInit(0.U((log2Up(latency)+1).W)) 30// 31// ready := (cnt < latency.U) || (cnt === latency.U && io.out.ready) 32// cnt := cnt + io.in.fire() - io.out.fire() 33// 34// val valids = io.in.valid +: Array.fill(latency)(RegInit(false.B)) 35// for(i <- 1 to latency){ 36// when(ready){ valids(i) := valids(i-1) } 37// } 38// 39// def PipelineReg[T<:Data](i: Int)(next: T) = RegEnable(next, enable = valids(i-1) && ready) 40// def S1Reg[T<:Data](next: T):T = PipelineReg[T](1)(next) 41// def S2Reg[T<:Data](next: T):T = PipelineReg[T](2)(next) 42// def S3Reg[T<:Data](next: T):T = PipelineReg[T](3)(next) 43// def S4Reg[T<:Data](next: T):T = PipelineReg[T](4)(next) 44// def S5Reg[T<:Data](next: T):T = PipelineReg[T](5)(next) 45// 46// io.in.ready := ready 47// io.out.valid := valids.last 48//} 49 50trait HasUIntToSIntHelper { 51 implicit class UIntToSIntHelper(x: UInt){ 52 def toSInt: SInt = Cat(0.U(1.W), x).asSInt() 53 } 54} 55 56//abstract class FPUSubModule extends Module with HasUIntToSIntHelper { 57// val io = IO(new FPUSubModuleIO) 58//} 59 60class FPUExtraInput extends Bundle { 61 val op = UInt(3.W) 62 val isDouble = Bool() 63 val rm = UInt(3.W) 64} 65 66trait HasFPUSigs { this: FPUSubModule => 67 val extraIn = io.in.bits.ext.get 68 val op = extraIn.op 69 val isDouble = extraIn.isDouble 70 val rm = extraIn.rm 71 val fflags = io.out.bits.ext.get 72} 73 74abstract class FPUSubModule(cfg: FuConfig, latency: Int = 0) extends FunctionUnit( 75 cfg, 76 latency = latency, 77 extIn = new FPUExtraInput, 78 extOut = new Fflags 79) with HasUIntToSIntHelper 80 with HasFPUSigs 81 82abstract class FPUPipelineModule(cfg: FuConfig, latency: Int) 83 extends FPUSubModule(cfg, latency) 84 with HasPipelineReg[FPUExtraInput, Fflags]