1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan.backend.fu.fpu 17 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import xiangshan.{FPUCtrlSignals, XSModule} 22import xiangshan.backend.fu.{FunctionUnit, HasPipelineReg} 23 24trait HasUIntToSIntHelper { 25 implicit class UIntToSIntHelper(x: UInt){ 26 def toSInt: SInt = Cat(0.U(1.W), x).asSInt() 27 } 28} 29 30abstract class FPUDataModule(implicit p: Parameters) extends XSModule { 31 val io = IO(new Bundle() { 32 val in = Input(new Bundle() { 33 val src = Vec(3, UInt(65.W)) 34 val fpCtrl = new FPUCtrlSignals 35 val rm = UInt(3.W) 36 }) 37 val out = Output(new Bundle() { 38 val data = UInt(65.W) 39 val fflags = UInt(5.W) 40 }) 41 }) 42 43 val rm = io.in.rm 44 val fflags = io.out.fflags 45} 46 47abstract class FPUSubModule(implicit p: Parameters) extends FunctionUnit(len = 65) 48 with HasUIntToSIntHelper 49{ 50 val rm = IO(Input(UInt(3.W))) 51 val fflags = IO(Output(UInt(5.W))) 52 val dataModule: FPUDataModule 53 def connectDataModule = { 54 dataModule.io.in.src <> io.in.bits.src 55 dataModule.io.in.fpCtrl <> io.in.bits.uop.ctrl.fpu 56 dataModule.io.in.rm <> rm 57 io.out.bits.data := dataModule.io.out.data 58 fflags := dataModule.io.out.fflags 59 } 60} 61 62abstract class FPUPipelineModule(implicit p: Parameters) 63 extends FPUSubModule 64 with HasPipelineReg 65