1package xiangshan.backend.fu.fpu 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan.backend.fu.{FuConfig, FunctionUnit, HasPipelineReg} 6 7 8class FPUSubModuleInput extends Bundle{ 9 val op = UInt(3.W) 10 val isDouble = Bool() 11 val a, b, c = UInt(64.W) 12 val rm = UInt(3.W) 13} 14 15class FPUSubModuleOutput extends Bundle{ 16 val fflags = new Fflags 17 val result = UInt(64.W) 18} 19 20class FPUSubModuleIO extends Bundle{ 21 val in = Flipped(DecoupledIO(new FPUSubModuleInput)) 22 val out = DecoupledIO(new FPUSubModuleOutput) 23} 24 25trait HasUIntToSIntHelper { 26 implicit class UIntToSIntHelper(x: UInt){ 27 def toSInt: SInt = Cat(0.U(1.W), x).asSInt() 28 } 29} 30 31trait HasFPUSigs { this: FPUSubModule => 32 val op = io.in.bits.uop.ctrl.fuOpType(2, 0) 33 // 'op' must change with fuOpType 34 require(io.in.bits.uop.ctrl.fuOpType.getWidth == 7) 35 val isDouble = !io.in.bits.uop.ctrl.isRVF 36} 37 38abstract class FPUSubModule extends FunctionUnit 39 with HasUIntToSIntHelper 40 with HasFPUSigs 41{ 42 val rm = IO(Input(UInt(3.W))) 43 val fflags = IO(Output(new Fflags)) 44} 45 46abstract class FPUPipelineModule 47 extends FPUSubModule 48 with HasPipelineReg