1package xiangshan.backend.fu.util 2 3import chisel3._ 4import org.chipsalliance.cde.config.Parameters 5import CSRConst.ModeM 6 7trait DebugCSR { 8 implicit val p: Parameters 9 class DcsrStruct extends Bundle { 10 val debugver = Output(UInt(4.W)) // [28:31] 11 val pad1 = Output(UInt(10.W))// [27:18] 12 val ebreakvs = Output(Bool()) // [17] reserved for Hypervisor debug 13 val ebreakvu = Output(Bool()) // [16] reserved for Hypervisor debug 14 val ebreakm = Output(Bool()) // [15] 15 val pad0 = Output(Bool()) // [14] ebreakh has been removed 16 val ebreaks = Output(Bool()) // [13] 17 val ebreaku = Output(Bool()) // [12] 18 val stepie = Output(Bool()) // [11] 19 val stopcount = Output(Bool()) // [10] 20 val stoptime = Output(Bool()) // [9] 21 val cause = Output(UInt(3.W)) // [8:6] 22 val v = Output(Bool()) // [5] 23 val mprven = Output(Bool()) // [4] 24 val nmip = Output(Bool()) // [3] 25 val step = Output(Bool()) // [2] 26 val prv = Output(UInt(2.W)) // [1:0] 27 require(this.getWidth == 32) 28 } 29 30 object DcsrStruct extends DcsrStruct { 31 def DEBUGVER_NONE = 0.U 32 def DEBUGVER_SPEC = 4.U 33 def DEBUGVER_CUSTOM = 15.U 34 def CAUSE_EBREAK = 1.U 35 def CAUSE_TRIGGER = 2.U 36 def CAUSE_HALTREQ = 3.U 37 def CAUSE_STEP = 4.U 38 def CAUSE_RESETHALTREQ = 5.U 39 private def debugver_offset = 28 40 private def stopcount_offset = 10 41 private def stoptime_offset = 9 42 private def mprven_offset = 5 43 private def prv_offset = 0 44 def init: UInt = ( 45 (DEBUGVER_SPEC.litValue << debugver_offset) | /* Debug implementation as it described in 0.13 draft */ 46 (0L << stopcount_offset) | /* Stop count updating has not been supported */ 47 (0L << stoptime_offset) | /* Stop time updating has not been supported */ 48 (0L << mprven_offset) | /* Whether use mstatus.perven as mprven */ 49 (ModeM.litValue << prv_offset) 50 ).U 51 } 52} 53 54