1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.log2Up 6import utility.SignExt 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.backend.fu.{BranchModule, FuConfig, FuncUnit} 9import xiangshan.backend.datapath.DataConfig.VAddrData 10import xiangshan.{RedirectLevel, SelImm, XSModule} 11 12class AddrAddModule(implicit p: Parameters) extends XSModule { 13 val io = IO(new Bundle { 14 val pc = Input(UInt(VAddrBits.W)) 15 val taken = Input(Bool()) 16 val isRVC = Input(Bool()) 17 val imm = Input(UInt(32.W)) // branch inst only support 12 bits immediate num 18 val target = Output(UInt(XLEN.W)) 19 val nextPcOffset = Input(UInt((log2Up(PredictWidth) + 1).W)) 20 }) 21 val pcExtend = SignExt(io.pc, VAddrBits + 1) 22 val immMinWidth = FuConfig.BrhCfg.immType.map(x => SelImm.getImmUnion(x).len).max 23 print(s"[Branch]: immMinWidth = $immMinWidth\n") 24 io.target := SignExt(Mux(io.taken, 25 pcExtend + SignExt(io.imm(immMinWidth + 2, 0), VAddrBits + 1), 26 pcExtend + (io.nextPcOffset << instOffsetBits).asUInt 27 ), XLEN) 28} 29 30class BranchUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) { 31 val dataModule = Module(new BranchModule) 32 val addModule = Module(new AddrAddModule) 33 dataModule.io.src(0) := io.in.bits.data.src(0) // rs1 34 dataModule.io.src(1) := io.in.bits.data.src(1) // rs2 35 dataModule.io.func := io.in.bits.ctrl.fuOpType 36 dataModule.io.pred_taken := io.in.bits.ctrl.predictInfo.get.taken 37 38 addModule.io.pc := io.in.bits.data.pc.get // pc 39 addModule.io.imm := io.in.bits.data.imm // imm 40 addModule.io.taken := dataModule.io.taken 41 addModule.io.isRVC := io.in.bits.ctrl.preDecode.get.isRVC 42 addModule.io.nextPcOffset := io.in.bits.data.nextPcOffset.get 43 44 io.out.valid := io.in.valid 45 io.in.ready := io.out.ready 46 47 io.out.bits.res.data := 0.U 48 io.out.bits.res.redirect.get match { 49 case redirect => 50 redirect.valid := io.out.valid && dataModule.io.mispredict 51 redirect.bits := 0.U.asTypeOf(io.out.bits.res.redirect.get.bits) 52 redirect.bits.level := RedirectLevel.flushAfter 53 redirect.bits.robIdx := io.in.bits.ctrl.robIdx 54 redirect.bits.ftqIdx := io.in.bits.ctrl.ftqIdx.get 55 redirect.bits.ftqOffset := io.in.bits.ctrl.ftqOffset.get 56 redirect.bits.fullTarget := addModule.io.target 57 redirect.bits.cfiUpdate.isMisPred := dataModule.io.mispredict 58 redirect.bits.cfiUpdate.taken := dataModule.io.taken 59 redirect.bits.cfiUpdate.predTaken := dataModule.io.pred_taken 60 redirect.bits.cfiUpdate.target := addModule.io.target 61 redirect.bits.cfiUpdate.pc := io.in.bits.data.pc.get 62 redirect.bits.cfiUpdate.backendIAF := io.instrAddrTransType.get.checkAccessFault(addModule.io.target) 63 redirect.bits.cfiUpdate.backendIPF := io.instrAddrTransType.get.checkPageFault(addModule.io.target) 64 redirect.bits.cfiUpdate.backendIGPF := io.instrAddrTransType.get.checkGuestPageFault(addModule.io.target) 65 } 66 connect0LatencyCtrlSingal 67} 68