1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.ExceptionNO._ 14import xiangshan.backend.Bundles.TrapInstInfo 15import xiangshan.backend.decode.Imm_Z 16import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 17import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 18import xiangshan.backend.rob.RobPtr 19import xiangshan.frontend.FtqPtr 20import CSRConst._ 21 22class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 23 with HasCircularQueuePtrHelper with HasCriticalErrors with HasSoCParameter 24{ 25 val csrIn = io.csrio.get 26 val csrOut = io.csrio.get 27 val csrToDecode = io.csrToDecode.get 28 29 val setFsDirty = csrIn.fpu.dirty_fs 30 val setFflags = csrIn.fpu.fflags 31 32 val setVsDirty = csrIn.vpu.dirty_vs 33 val setVstart = csrIn.vpu.set_vstart 34 val setVtype = csrIn.vpu.set_vtype 35 val setVxsat = csrIn.vpu.set_vxsat 36 val vlFromPreg = csrIn.vpu.vl 37 38 val flushPipe = Wire(Bool()) 39 val flush = io.flush.valid 40 41 /** Alias of input signals */ 42 val (valid, src1, imm, func) = ( 43 io.in.valid, 44 io.in.bits.data.src(0), 45 io.in.bits.data.imm(Imm_Z().len - 1, 0), 46 io.in.bits.ctrl.fuOpType 47 ) 48 49 // split imm/src1/rd from IMM_Z: src1/rd for tval 50 val addr = Imm_Z().getCSRAddr(imm) 51 val rd = Imm_Z().getRD(imm) 52 val rs1 = Imm_Z().getRS1(imm) 53 val imm5 = Imm_Z().getImm5(imm) 54 val csri = ZeroExt(imm5, XLEN) 55 56 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 57 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 58 private val isMNret = CSROpType.isSystemOp(func) && addr === privMNret 59 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 60 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 61 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 62 private val isWfi = CSROpType.isWfi(func) 63 private val isCSRAcc = CSROpType.isCsrAccess(func) 64 65 val csrMod = Module(new NewCSR) 66 val trapInstMod = Module(new TrapInstMod) 67 val trapTvalMod = Module(new TrapTvalMod) 68 69 private val privState = csrMod.io.status.privState 70 // The real reg value in CSR, with no read mask 71 private val regOut = csrMod.io.out.bits.regOut 72 private val src = Mux(CSROpType.needImm(func), csri, src1) 73 private val wdata = LookupTree(func, Seq( 74 CSROpType.wrt -> src1, 75 CSROpType.set -> (regOut | src1), 76 CSROpType.clr -> (regOut & (~src1).asUInt), 77 CSROpType.wrti -> csri, 78 CSROpType.seti -> (regOut | csri), 79 CSROpType.clri -> (regOut & (~csri).asUInt), 80 )) 81 82 private val csrAccess = valid && CSROpType.isCsrAccess(func) 83 private val csrWen = valid && ( 84 CSROpType.isCSRRW(func) || 85 CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U 86 ) 87 private val csrRen = valid && ( 88 CSROpType.isCSRRW(func) && rd =/= 0.U || 89 CSROpType.isCSRRSorRC(func) 90 ) 91 92 private val waddrReg = RegEnable(addr, 0.U(12.W), io.in.fire) 93 private val wdataReg = RegEnable(wdata, 0.U(64.W), io.in.fire) 94 95 private val robIdxReg = RegEnable(io.in.bits.ctrl.robIdx, io.in.fire) 96 private val thisRobIdx = Wire(new RobPtr) 97 when (io.in.valid) { 98 thisRobIdx := io.in.bits.ctrl.robIdx 99 }.otherwise { 100 thisRobIdx := robIdxReg 101 } 102 private val redirectFlush = thisRobIdx.needFlush(io.flush) 103 104 csrMod.io.in match { 105 case in => 106 in.valid := valid 107 in.bits.wen := csrWen 108 in.bits.ren := csrRen 109 in.bits.op := CSROpType.getCSROp(func) 110 in.bits.addr := addr 111 in.bits.src := src 112 in.bits.wdata := wdataReg 113 in.bits.mret := isMret 114 in.bits.mnret := isMNret 115 in.bits.sret := isSret 116 in.bits.dret := isDret 117 in.bits.redirectFlush := redirectFlush 118 } 119 csrMod.io.trapInst := trapInstMod.io.currentTrapInst 120 csrMod.io.fetchMalTval := trapTvalMod.io.tval 121 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 122 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 123 csrMod.io.fromMem.excpIsForVSnonLeafPTE := csrIn.memExceptionIsForVSnonLeafPTE 124 125 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 126 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 127 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 128 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 129 // Todo: shrink the width of trap vector. 130 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 131 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 132 csrMod.io.fromRob.trap.bits.isFetchBkpt := csrIn.exception.bits.isPcBkpt 133 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 134 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 135 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 136 csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger 137 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 138 csrMod.io.fromRob.trap.bits.isFetchMalAddr := csrIn.exception.bits.isFetchMalAddr 139 csrMod.io.fromRob.trap.bits.isForVSnonLeafPTE := csrIn.exception.bits.isForVSnonLeafPTE 140 141 csrMod.io.fromRob.commit.fflags := setFflags 142 csrMod.io.fromRob.commit.fsDirty := setFsDirty 143 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 144 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 145 csrMod.io.fromRob.commit.vsDirty := setVsDirty 146 csrMod.io.fromRob.commit.vstart := setVstart 147 csrMod.io.fromRob.commit.vl := vlFromPreg 148 // Todo: correct vtype 149 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 150 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 151 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 152 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 153 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 154 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 155 156 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 157 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 158 159 csrMod.io.fromRob.robDeqPtr := csrIn.robDeqPtr 160 161 csrMod.io.fromVecExcpMod.busy := io.csrin.get.fromVecExcpMod.busy 162 163 csrMod.io.perf := csrIn.perf 164 165 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 166 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 167 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 168 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 169 csrMod.platformIRP.STIP := false.B 170 csrMod.platformIRP.VSEIP := false.B // Todo 171 csrMod.platformIRP.VSTIP := false.B // Todo 172 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 173 csrMod.nonMaskableIRP.NMI_43 := csrIn.externalInterrupt.nmi.nmi_43 174 csrMod.nonMaskableIRP.NMI_31 := csrIn.externalInterrupt.nmi.nmi_31 175 176 csrMod.io.fromTop.hartId := io.csrin.get.hartId 177 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 178 csrMod.io.fromTop.l2FlushDone := io.csrin.get.l2FlushDone 179 csrMod.io.fromTop.criticalErrorState := io.csrin.get.criticalErrorState 180 private val csrModOutValid = csrMod.io.out.valid 181 private val csrModOut = csrMod.io.out.bits 182 183 trapInstMod.io.fromDecode.trapInstInfo := RegNextWithEnable(io.csrin.get.trapInstInfo, hasInit = true) 184 trapInstMod.io.fromRob.flush.valid := io.flush.valid 185 trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx 186 trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset 187 trapInstMod.io.faultCsrUop.valid := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI) 188 trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire) 189 trapInstMod.io.faultCsrUop.bits.imm := DataHoldBypass(io.in.bits.data.imm, io.in.fire) 190 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqPtr := DataHoldBypass(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 191 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqOffset := DataHoldBypass(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 192 // Clear trap instruction when instruction fault trap(EX_II, EX_VI) occurs. 193 trapInstMod.io.readClear := (csrMod.io.fromRob.trap match { 194 case t => 195 t.valid && !t.bits.isInterrupt && (t.bits.trapVec(EX_II) || t.bits.trapVec(EX_VI)) 196 }) 197 198 trapTvalMod.io.targetPc.valid := csrMod.io.out.bits.targetPcUpdate 199 trapTvalMod.io.targetPc.bits := csrMod.io.out.bits.targetPc 200 trapTvalMod.io.clear := csrIn.exception.valid && csrIn.exception.bits.isFetchMalAddr 201 trapTvalMod.io.fromCtrlBlock.flush := io.flush 202 trapTvalMod.io.fromCtrlBlock.robDeqPtr := io.csrio.get.robDeqPtr 203 204 val imsic = Module(new aia.IMSIC(soc.IMSICParams)) 205 imsic.fromCSR.addr.valid := csrMod.toAIA.addr.valid 206 imsic.fromCSR.addr.bits.addr := csrMod.toAIA.addr.bits.addr 207 imsic.fromCSR.addr.bits.virt := csrMod.toAIA.addr.bits.v.asUInt.asBool 208 imsic.fromCSR.addr.bits.priv := aia.PrivType(csrMod.toAIA.addr.bits.prvm.asUInt) 209 imsic.fromCSR.vgein := csrMod.toAIA.vgein 210 imsic.fromCSR.wdata.valid := csrMod.toAIA.wdata.valid 211 imsic.fromCSR.wdata.bits.op := aia.OpType(csrMod.toAIA.wdata.bits.op) 212 imsic.fromCSR.wdata.bits.data := csrMod.toAIA.wdata.bits.data 213 imsic.fromCSR.claims(0) := csrMod.toAIA.mClaim 214 imsic.fromCSR.claims(1) := csrMod.toAIA.sClaim 215 imsic.fromCSR.claims(2) := csrMod.toAIA.vsClaim 216 217 csrMod.fromAIA.rdata.valid := imsic.toCSR.rdata.valid 218 csrMod.fromAIA.rdata.bits.data := imsic.toCSR.rdata.bits 219 csrMod.fromAIA.rdata.bits.illegal := imsic.toCSR.illegal 220 csrMod.fromAIA.meip := imsic.toCSR.pendings(0) 221 csrMod.fromAIA.seip := imsic.toCSR.pendings(1) 222 csrMod.fromAIA.vseip := imsic.toCSR.pendings(soc.IMSICParams.intFilesNum - 1, 2) 223 csrMod.fromAIA.mtopei := imsic.toCSR.topeis(0) 224 csrMod.fromAIA.stopei := imsic.toCSR.topeis(1) 225 csrMod.fromAIA.vstopei := imsic.toCSR.topeis(2) 226 227 imsic.msiio.vld_req := io.csrin.get.msiInfo.valid 228 imsic.msiio.data := io.csrin.get.msiInfo.bits 229 io.csrio.get.msiAck := imsic.msiio.vld_ack 230 231 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 232 233 exceptionVec(EX_BP ) := DataHoldBypass(isEbreak, false.B, io.in.fire) 234 exceptionVec(EX_MCALL ) := DataHoldBypass(isEcall && privState.isModeM, false.B, io.in.fire) 235 exceptionVec(EX_HSCALL) := DataHoldBypass(isEcall && privState.isModeHS, false.B, io.in.fire) 236 exceptionVec(EX_VSCALL) := DataHoldBypass(isEcall && privState.isModeVS, false.B, io.in.fire) 237 exceptionVec(EX_UCALL ) := DataHoldBypass(isEcall && privState.isModeHUorVU, false.B, io.in.fire) 238 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 239 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 240 241 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 242 243 flushPipe := csrMod.io.out.bits.flushPipe 244 245 // tlb 246 val tlb = Wire(new TlbCsrBundle) 247 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 248 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 249 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 250 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 251 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 252 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 253 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 254 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 255 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 256 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 257 tlb.hgatp.vmid := csrMod.io.tlb.hgatp.VMID.asUInt 258 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 259 tlb.mbmc.BME := csrMod.io.tlb.mbmc.BME.asUInt 260 tlb.mbmc.CMODE := csrMod.io.tlb.mbmc.CMODE.asUInt 261 tlb.mbmc.BCLEAR := csrMod.io.tlb.mbmc.BCLEAR.asUInt 262 tlb.mbmc.BMA := csrMod.io.tlb.mbmc.BMA.asUInt 263 264 // expose several csr bits for tlb 265 tlb.priv.mxr := csrMod.io.tlb.mxr 266 tlb.priv.sum := csrMod.io.tlb.sum 267 tlb.priv.vmxr := csrMod.io.tlb.vmxr 268 tlb.priv.vsum := csrMod.io.tlb.vsum 269 tlb.priv.spvp := csrMod.io.tlb.spvp 270 tlb.priv.virt := csrMod.io.tlb.dvirt 271 tlb.priv.imode := csrMod.io.tlb.imode 272 tlb.priv.dmode := csrMod.io.tlb.dmode 273 274 // Svpbmt extension enable 275 tlb.mPBMTE := csrMod.io.tlb.mPBMTE 276 tlb.hPBMTE := csrMod.io.tlb.hPBMTE 277 278 // pointer masking extension 279 tlb.pmm := csrMod.io.tlb.pmm 280 281 /** Since some CSR read instructions are allowed to be pipelined, ready/valid signals should be modified */ 282 io.in.ready := csrMod.io.in.ready // Todo: Async read imsic may block CSR 283 io.out.valid := csrModOutValid 284 io.out.bits.ctrl.exceptionVec.get := exceptionVec 285 io.out.bits.ctrl.flushPipe.get := flushPipe 286 io.out.bits.res.data := csrMod.io.out.bits.rData 287 288 /** initialize NewCSR's io_out_ready from wrapper's io */ 289 csrMod.io.out.ready := io.out.ready 290 291 io.out.bits.res.redirect.get.valid := io.out.valid && RegEnable(isXRet, false.B, io.in.fire) 292 val redirect = io.out.bits.res.redirect.get.bits 293 redirect := 0.U.asTypeOf(redirect) 294 redirect.level := RedirectLevel.flushAfter 295 redirect.robIdx := robIdxReg 296 redirect.ftqIdx := RegEnable(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 297 redirect.ftqOffset := RegEnable(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 298 redirect.cfiUpdate.predTaken := true.B 299 redirect.cfiUpdate.taken := true.B 300 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc.pc 301 redirect.cfiUpdate.backendIPF := csrMod.io.out.bits.targetPc.raiseIPF 302 redirect.cfiUpdate.backendIAF := csrMod.io.out.bits.targetPc.raiseIAF 303 redirect.cfiUpdate.backendIGPF := csrMod.io.out.bits.targetPc.raiseIGPF 304 // Only mispred will send redirect to frontend 305 redirect.cfiUpdate.isMisPred := true.B 306 307 connectNonPipedCtrlSingal 308 309 override val criticalErrors = csrMod.getCriticalErrors 310 generateCriticalErrors() 311 312 // Todo: summerize all difftest skip condition 313 csrOut.isPerfCnt := io.out.valid && csrMod.io.out.bits.isPerfCnt && RegEnable(func =/= CSROpType.jmp, false.B, io.in.fire) 314 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 315 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 316 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 317 318 csrOut.isXRet := isXRet 319 320 csrOut.trapTarget := csrMod.io.out.bits.targetPc 321 csrOut.interrupt := csrMod.io.status.interrupt 322 csrOut.wfi_event := csrMod.io.status.wfiEvent 323 324 csrOut.tlb := tlb 325 326 csrOut.debugMode := csrMod.io.status.debugMode 327 328 csrOut.traceCSR := csrMod.io.status.traceCSR 329 330 csrOut.customCtrl match { 331 case custom => 332 custom.pf_ctrl := csrMod.io.status.custom.pf_ctrl 333 // Load violation predictor 334 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 335 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 336 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 337 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 338 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 339 // Branch predictor 340 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 341 // Memory Block 342 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 343 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 344 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 345 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 346 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 347 custom.hd_misalign_st_enable := csrMod.io.status.custom.hd_misalign_st_enable 348 custom.hd_misalign_ld_enable := csrMod.io.status.custom.hd_misalign_ld_enable 349 custom.power_down_enable := csrMod.io.status.custom.power_down_enable 350 custom.flush_l2_enable := csrMod.io.status.custom.flush_l2_enable 351 // Rename 352 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 353 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 354 // distribute csr write signal 355 // write to frontend and memory 356 custom.distribute_csr.w.valid := csrMod.io.distributedWenLegal 357 custom.distribute_csr.w.bits.addr := waddrReg 358 custom.distribute_csr.w.bits.data := wdataReg 359 // rename single step 360 custom.singlestep := csrMod.io.status.singleStepFlag 361 // trigger 362 custom.frontend_trigger := csrMod.io.status.frontendTrigger 363 custom.mem_trigger := csrMod.io.status.memTrigger 364 // virtual mode 365 custom.virtMode := csrMod.io.status.privState.V.asBool 366 // xstatus.fs field is off 367 custom.fsIsOff := csrMod.io.toDecode.illegalInst.fsIsOff 368 } 369 370 csrOut.instrAddrTransType := csrMod.io.status.instrAddrTransType 371 csrOut.criticalErrorState := csrMod.io.status.criticalErrorState 372 373 csrToDecode := csrMod.io.toDecode 374} 375 376class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter { 377 val hartId = Input(UInt(8.W)) 378 val msiInfo = Input(ValidIO(UInt(soc.IMSICParams.MSI_INFO_WIDTH.W))) 379 val criticalErrorState = Input(Bool()) 380 val clintTime = Input(ValidIO(UInt(64.W))) 381 val l2FlushDone = Input(Bool()) 382 val trapInstInfo = Input(ValidIO(new TrapInstInfo)) 383 val fromVecExcpMod = Input(new Bundle { 384 val busy = Bool() 385 }) 386} 387 388class CSRToDecode(implicit p: Parameters) extends XSBundle { 389 val illegalInst = new Bundle { 390 /** 391 * illegal sfence.vma, sinval.vma 392 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 393 */ 394 val sfenceVMA = Bool() 395 396 /** 397 * illegal sfence.w.inval sfence.inval.ir 398 * raise EX_II when isModeHU 399 */ 400 val sfencePart = Bool() 401 402 /** 403 * illegal hfence.gvma, hinval.gvma 404 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 405 * the condition is the same as sfenceVMA 406 */ 407 val hfenceGVMA = Bool() 408 409 /** 410 * illegal hfence.vvma, hinval.vvma 411 * raise EX_II when isModeHU 412 */ 413 val hfenceVVMA = Bool() 414 415 /** 416 * illegal hlv, hlvx, and hsv 417 * raise EX_II when isModeHU && hstatus.HU=0 418 */ 419 val hlsv = Bool() 420 421 /** 422 * decode all fp inst or all vecfp inst 423 * raise EX_II when FS=Off 424 */ 425 val fsIsOff = Bool() 426 427 /** 428 * decode all vec inst 429 * raise EX_II when VS=Off 430 */ 431 val vsIsOff = Bool() 432 433 /** 434 * illegal wfi 435 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 436 */ 437 val wfi = Bool() 438 439 /** 440 * illegal wrs_nto 441 * raise EX_II when !isModeM && mstatus.TW=1 442 */ 443 val wrs_nto = Bool() 444 445 /** 446 * frm reserved 447 * raise EX_II when frm.data > 4 448 */ 449 val frm = Bool() 450 451 /** 452 * illegal CBO.ZERO 453 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBZE || isModeHU && !SEnvCfg.CBZE 454 */ 455 val cboZ = Bool() 456 457 /** 458 * illegal CBO.CLEAN/FLUSH 459 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBCFE || isModeHU && !SEnvCfg.CBCFE 460 */ 461 val cboCF = Bool() 462 463 /** 464 * illegal CBO.INVAL 465 * raise [[EX_II]] when !isModeM && MEnvCfg.CBIE = EnvCBIE.Off || isModeHU && SEnvCfg.CBIE = EnvCBIE.Off 466 */ 467 val cboI = Bool() 468 } 469 470 val virtualInst = new Bundle { 471 /** 472 * illegal sfence.vma, svinval.vma 473 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 474 */ 475 val sfenceVMA = Bool() 476 477 /** 478 * illegal sfence.w.inval sfence.inval.ir 479 * raise EX_VI when isModeVU 480 */ 481 val sfencePart = Bool() 482 483 /** 484 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 485 * raise EX_VI when isModeVS || isModeVU 486 */ 487 val hfence = Bool() 488 489 /** 490 * illegal hlv, hlvx, and hsv 491 * raise EX_VI when isModeVS || isModeVU 492 */ 493 val hlsv = Bool() 494 495 /** 496 * illegal wfi 497 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 498 */ 499 val wfi = Bool() 500 501 /** 502 * illegal wrs_nto 503 * raise EX_VI when privState.V && mstatus.TW=0 && hstatus.VTW=1 504 */ 505 val wrs_nto = Bool() 506 507 /** 508 * illegal CBO.ZERO 509 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBZE || isModeVU && (!HEnvCfg.CBZE || !SEnvCfg.CBZE)) 510 */ 511 val cboZ = Bool() 512 513 /** 514 * illegal CBO.CLEAN/FLUSH 515 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBCFE || isModeVU && (!HEnvCfg.CBCFE || !SEnvCfg.CBCFE)) 516 */ 517 val cboCF = Bool() 518 519 /** 520 * illegal CBO.INVAL <br/> 521 * raise [[EX_VI]] when MEnvCfg.CBIE =/= EnvCBIE.Off && ( <br/> 522 * isModeVS && HEnvCfg.CBIE === EnvCBIE.Off || <br/> 523 * isModeVU && (HEnvCfg.CBIE === EnvCBIE.Off || SEnvCfg.CBIE === EnvCBIE.Off) <br/> 524 * ) <br/> 525 */ 526 val cboI = Bool() 527 } 528 529 val special = new Bundle { 530 /** 531 * execute CBO.INVAL and perform flush operation when <br/> 532 * isModeHS && MEnvCfg.CBIE === EnvCBIE.Flush || <br/> 533 * isModeHU && (MEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 534 * isModeVS && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush) <br/> 535 * isModeVU && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 536 */ 537 val cboI2F = Bool() 538 } 539}