1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3.{VecInit, _} 5import chisel3.util._ 6import chisel3.util.experimental.decode.{QMCMinimizer, TruthTable, decoder} 7import utility.{DelayN, XSError} 8import xiangshan.XSCoreParamsKey 9import xiangshan.backend.fu.vector.Bundles.{VConfig, VSew} 10import xiangshan.backend.fu.vector.{Mgu, Mgtu, VecPipedFuncUnit} 11import xiangshan.backend.fu.vector.Utils.VecDataToMaskDataVec 12import xiangshan.backend.fu.vector.utils.VecDataSplitModule 13import xiangshan.backend.fu.{FuConfig, FuType} 14import xiangshan.ExceptionNO 15import yunsuan.{OpType, VialuFixType} 16import yunsuan.vector.alu.{VIntFixpAlu64b, VIntFixpDecode, VIntFixpTable} 17import yunsuan.encoding.{VdType, Vs1IntType, Vs2IntType} 18import yunsuan.encoding.Opcode.VialuOpcode 19import yunsuan.vector.SewOH 20 21class VIAluSrcTypeIO extends Bundle { 22 val in = Input(new Bundle { 23 val fuOpType: UInt = OpType() 24 val vsew: UInt = VSew() 25 val isReverse: Bool = Bool() // vrsub, vrdiv 26 val isExt: Bool = Bool() 27 val isDstMask: Bool = Bool() // vvm, vvvm, mmm 28 val isMove: Bool = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 29 }) 30 val out = Output(new Bundle { 31 val vs1Type: UInt = Vs1IntType() 32 val vs2Type: UInt = Vs2IntType() 33 val vdType: UInt = VdType() 34 val illegal: Bool = Bool() 35 val isVextF2: Bool = Bool() 36 val isVextF4: Bool = Bool() 37 val isVextF8: Bool = Bool() 38 }) 39} 40 41class VIAluSrcTypeModule extends Module { 42 val io: VIAluSrcTypeIO = IO(new VIAluSrcTypeIO) 43 44 private val vsew = io.in.vsew 45 private val isExt = io.in.isExt 46 private val isDstMask = io.in.isDstMask 47 48 private val opcode = VialuFixType.getOpcode(io.in.fuOpType) 49 private val isSign = VialuFixType.isSigned(io.in.fuOpType) 50 private val format = VialuFixType.getFormat(io.in.fuOpType) 51 52 private val vsewX2 = vsew + 1.U 53 private val vsewF2 = vsew - 1.U 54 private val vsewF4 = vsew - 2.U 55 private val vsewF8 = vsew - 3.U 56 57 private val isAddSub = opcode === VialuOpcode.vadd || opcode === VialuOpcode.vsub 58 private val isShiftRight = Seq(VialuOpcode.vsrl, VialuOpcode.vsra, VialuOpcode.vssrl, VialuOpcode.vssra).map(fmt => fmt === format).reduce(_ || _) 59 private val isVext = opcode === VialuOpcode.vext 60 61 private val isWiden = isAddSub && Seq(VialuFixType.FMT.VVW, VialuFixType.FMT.WVW).map(fmt => fmt === format).reduce(_ || _) 62 private val isNarrow = isShiftRight && format === VialuFixType.FMT.WVV 63 private val isVextF2 = isVext && format === VialuFixType.FMT.VF2 64 private val isVextF4 = isVext && format === VialuFixType.FMT.VF4 65 private val isVextF8 = isVext && format === VialuFixType.FMT.VF8 66 67 // check illegal 68 private val widenIllegal = isWiden && vsewX2 === VSew.e8 69 private val narrowIllegal = isNarrow && vsewF2 === VSew.e64 70 private val vextIllegal = (isVextF2 && (vsewF2 === VSew.e64)) || 71 (isVextF4 && (vsewF4 === VSew.e64)) || 72 (isVextF8 && (vsewF8 === VSew.e64)) 73 // Todo: use it 74 private val illegal = widenIllegal || narrowIllegal || vextIllegal 75 76 private val intType = Cat(0.U(1.W), isSign) 77 78 private class Vs2Vs1VdSew extends Bundle { 79 val vs2 = VSew() 80 val vs1 = VSew() 81 val vd = VSew() 82 } 83 84 private class Vs2Vs1VdType extends Bundle { 85 val vs2 = Vs2IntType() 86 val vs1 = Vs1IntType() 87 val vd = VdType() 88 } 89 90 private val addSubSews = Mux1H(Seq( 91 (format === VialuFixType.FMT.VVV) -> Cat(vsew, vsew, vsew), 92 (format === VialuFixType.FMT.VVW) -> Cat(vsew, vsew, vsewX2), 93 (format === VialuFixType.FMT.WVW) -> Cat(vsewX2, vsew, vsewX2), 94 (format === VialuFixType.FMT.WVV) -> Cat(vsewX2, vsew, vsew), 95 )).asTypeOf(new Vs2Vs1VdSew) 96 97 private val vextSews = Mux1H(Seq( 98 (format === VialuFixType.FMT.VF2) -> Cat(vsewF2, vsewF2, vsew), 99 (format === VialuFixType.FMT.VF4) -> Cat(vsewF4, vsewF4, vsew), 100 (format === VialuFixType.FMT.VF8) -> Cat(vsewF8, vsewF8, vsew), 101 )).asTypeOf(new Vs2Vs1VdSew) 102 103 private val maskTypes = Mux1H(Seq( 104 (format === VialuFixType.FMT.VVM) -> Cat(Cat(intType, vsew), Cat(intType, vsew), VdType.mask), 105 (format === VialuFixType.FMT.VVMM) -> Cat(Cat(intType, vsew), Cat(intType, vsew), VdType.mask), 106 (format === VialuFixType.FMT.MMM) -> Cat(Vs2IntType.mask, Vs1IntType.mask, VdType.mask), 107 )).asTypeOf(new Vs2Vs1VdType) 108 109 private val vs2Type = Mux1H(Seq( 110 isDstMask -> maskTypes.vs2, 111 isExt -> Cat(intType, vextSews.vs2), 112 (!isExt && !isDstMask) -> Cat(intType, addSubSews.vs2), 113 )) 114 private val vs1Type = Mux1H(Seq( 115 isDstMask -> maskTypes.vs1, 116 isExt -> Cat(intType, vextSews.vs1), 117 (!isExt && !isDstMask) -> Cat(intType, addSubSews.vs1), 118 )) 119 private val vdType = Mux1H(Seq( 120 isDstMask -> maskTypes.vd, 121 isExt -> Cat(intType, vextSews.vd), 122 (!isExt && !isDstMask) -> Cat(intType, addSubSews.vd), 123 )) 124 125 io.out.vs2Type := vs2Type 126 io.out.vs1Type := vs1Type 127 io.out.vdType := vdType 128 io.out.illegal := illegal 129 io.out.isVextF2 := isVextF2 130 io.out.isVextF4 := isVextF4 131 io.out.isVextF8 := isVextF8 132} 133 134class VIAluFix(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 135 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VialuFixType.dummy, "VialuF OpType not supported") 136 137 // config params 138 private val dataWidth = cfg.destDataBits 139 private val dataWidthOfDataModule = 64 140 private val numVecModule = dataWidth / dataWidthOfDataModule 141 142 // modules 143 private val typeMod = Module(new VIAluSrcTypeModule) 144 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 145 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 146 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 147 private val vIntFixpAlus = Seq.fill(numVecModule)(Module(new VIntFixpAlu64b)) 148 private val mgu = Module(new Mgu(dataWidth)) 149 private val mgtu = Module(new Mgtu(dataWidth)) 150 151 /** 152 * [[typeMod]]'s in connection 153 */ 154 typeMod.io.in.fuOpType := fuOpType 155 typeMod.io.in.vsew := vsew 156 typeMod.io.in.isReverse := isReverse 157 typeMod.io.in.isExt := isExt 158 typeMod.io.in.isDstMask := vecCtrl.isDstMask 159 typeMod.io.in.isMove := isMove 160 161 private val vs2GroupedVec32b: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 162 private val vs2GroupedVec16b: Vec[UInt] = VecInit(vs2Split.io.outVec16b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 163 private val vs2GroupedVec8b : Vec[UInt] = VecInit(vs2Split.io.outVec8b .zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 164 private val vs1GroupedVec32b: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 165 private val vs1GroupedVec16b: Vec[UInt] = VecInit(vs1Split.io.outVec16b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 166 private val vs1GroupedVec8b : Vec[UInt] = VecInit(vs1Split.io.outVec8b .zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 167 168 /** 169 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 170 */ 171 vs2Split.io.inVecData := vs2 172 vs1Split.io.inVecData := vs1 173 oldVdSplit.io.inVecData := oldVd 174 175 /** 176 * [[vIntFixpAlus]]'s in connection 177 */ 178 private val opcode = VialuFixType.getOpcode(inCtrl.fuOpType).asTypeOf(vIntFixpAlus.head.io.opcode) 179 private val vs1Type = typeMod.io.out.vs1Type 180 private val vs2Type = typeMod.io.out.vs2Type 181 private val vdType = typeMod.io.out.vdType 182 private val isVextF2 = typeMod.io.out.isVextF2 183 private val isVextF4 = typeMod.io.out.isVextF4 184 private val isVextF8 = typeMod.io.out.isVextF8 185 186 private val truthTable = TruthTable(VIntFixpTable.table, VIntFixpTable.default) 187 private val decoderOut = decoder(QMCMinimizer, Cat(opcode.op), truthTable) 188 private val vIntFixpDecode = decoderOut.asTypeOf(new VIntFixpDecode) 189 private val isFixp = Mux(vIntFixpDecode.misc, opcode.isScalingShift, opcode.isSatAdd || opcode.isAvgAdd) 190 private val widen = opcode.isAddSub && vs1Type(1, 0) =/= vdType(1, 0) 191 private val widen_vs2 = widen && vs2Type(1, 0) =/= vdType(1, 0) 192 private val eewVs1 = SewOH(vs1Type(1, 0)) 193 private val eewVd = SewOH(vdType(1, 0)) 194 private val isVwsll = opcode.isVwsll 195 196 // Extension instructions 197 private val vf2 = isVextF2 198 private val vf4 = isVextF4 199 private val vf8 = isVextF8 200 201 private val vs1VecUsed: Vec[UInt] = Wire(Vec(numVecModule, UInt(64.W))) 202 private val vs2VecUsed: Vec[UInt] = Wire(Vec(numVecModule, UInt(64.W))) 203 private val isVwsllEewVdIs64 = isVwsll && eewVd.is64 204 private val isVwsllEewVdIs32 = isVwsll && eewVd.is32 205 private val isVwsllEewVdIs16 = isVwsll && eewVd.is16 206 when(widen || isNarrow || isVwsllEewVdIs64) { 207 vs1VecUsed := vs1GroupedVec32b 208 }.elsewhen(isVwsllEewVdIs32) { 209 vs1VecUsed := vs1GroupedVec16b 210 }.elsewhen(isVwsllEewVdIs16) { 211 vs1VecUsed := vs1GroupedVec8b 212 }.otherwise { 213 vs1VecUsed := vs1Split.io.outVec64b 214 } 215 when(vf2 || isVwsllEewVdIs64) { 216 vs2VecUsed := vs2GroupedVec32b 217 }.elsewhen(vf4 || isVwsllEewVdIs32) { 218 vs2VecUsed := vs2GroupedVec16b 219 }.elsewhen(vf8 || isVwsllEewVdIs16) { 220 vs2VecUsed := vs2GroupedVec8b 221 }.otherwise { 222 vs2VecUsed := vs2Split.io.outVec64b 223 } 224 225 private val vs2Adder = Mux(widen_vs2, vs2GroupedVec32b, vs2Split.io.outVec64b) 226 227 // mask 228 private val maskDataVec: Vec[UInt] = VecDataToMaskDataVec(srcMask, vsew) 229 private val maskIdx = Mux(isNarrow, (vuopIdx >> 1.U).asUInt, vuopIdx) 230 private val eewVd_is_1b = vdType === VdType.mask 231 private val maskUsed = splitMask(maskDataVec(maskIdx), Mux(eewVd_is_1b, eewVs1, eewVd)) 232 233 private val oldVdUsed = splitMask(VecDataToMaskDataVec(oldVd, vs1Type(1, 0))(vuopIdx), eewVs1) 234 235 vIntFixpAlus.zipWithIndex.foreach { 236 case (mod, i) => 237 mod.io.fire := io.in.valid 238 mod.io.opcode := opcode 239 240 mod.io.info.vm := vm 241 mod.io.info.ma := vma 242 mod.io.info.ta := vta 243 mod.io.info.vlmul := vlmul 244 mod.io.info.vl := vl 245 mod.io.info.vstart := vstart 246 mod.io.info.uopIdx := vuopIdx 247 mod.io.info.vxrm := vxrm 248 249 mod.io.srcType(0) := vs2Type 250 mod.io.srcType(1) := vs1Type 251 mod.io.vdType := vdType 252 mod.io.narrow := isNarrow 253 mod.io.isSub := vIntFixpDecode.sub 254 mod.io.isMisc := vIntFixpDecode.misc 255 mod.io.isFixp := isFixp 256 mod.io.widen := widen 257 mod.io.widen_vs2 := widen_vs2 258 mod.io.vs1 := vs1VecUsed(i) 259 mod.io.vs2_adder := vs2Adder(i) 260 mod.io.vs2_misc := vs2VecUsed(i) 261 mod.io.vmask := maskUsed(i) 262 mod.io.oldVd := oldVdUsed(i) 263 } 264 265 /** 266 * [[mgu]]'s in connection 267 */ 268 private val outIsVwsll = RegEnable(isVwsll, io.in.valid) 269 private val outIsVwsllEewVdIs64 = RegEnable(isVwsllEewVdIs64, io.in.valid) 270 private val outIsVwsllEewVdIs32 = RegEnable(isVwsllEewVdIs32, io.in.valid) 271 private val outIsVwsllEewVdIs16 = RegEnable(isVwsllEewVdIs16, io.in.valid) 272 //private val outEewVs1 = DelayN(eewVs1, latency) 273 private val outEewVs1 = SNReg(eewVs1, latency) 274 275 private val outVdTmp = Cat(vIntFixpAlus.reverse.map(_.io.vd)) 276 private val outVd = Mux1H(Seq( 277 (outIsVwsllEewVdIs64 || !outIsVwsll) -> outVdTmp, 278 outIsVwsllEewVdIs32 -> Cat(outVdTmp(127, 96), outVdTmp(63, 32), outVdTmp( 95, 64), outVdTmp(31, 0)), 279 outIsVwsllEewVdIs16 -> Cat(outVdTmp(127, 112), outVdTmp(63, 48), outVdTmp(111, 96), outVdTmp(47, 32), outVdTmp(95, 80), outVdTmp(31, 16), outVdTmp(79, 64), outVdTmp(15,0)), 280 )) 281 private val outCmp = Mux1H(outEewVs1.oneHot, Seq(8, 4, 2, 1).map( 282 k => Cat(vIntFixpAlus.reverse.map(_.io.cmpOut(k - 1, 0))))) 283 private val outNarrow = Cat(vIntFixpAlus.reverse.map(_.io.narrowVd)) 284 private val outOpcode = VialuFixType.getOpcode(outCtrl.fuOpType).asTypeOf(vIntFixpAlus.head.io.opcode) 285 286 private val numBytes = dataWidth / 8 287 private val maxMaskIdx = numBytes 288 private val maxVdIdx = 8 289 private val elementsInOneUop = Mux1H(outEewVs1.oneHot, Seq(1, 2, 4, 8).map(k => (numBytes / k).U(5.W))) 290 private val vdIdx = outVecCtrl.vuopIdx(2, 0) 291 private val elementsComputed = Mux1H(Seq.tabulate(maxVdIdx)(i => (vdIdx === i.U) -> (elementsInOneUop * i.U))) 292 val outCmpWithTail = Wire(Vec(maxMaskIdx, UInt(1.W))) 293 // set the bits in vd to 1 if the index is larger than vl and vta is true 294 for (i <- 0 until maxMaskIdx) { 295 when(elementsComputed +& i.U >= outVl) { 296 // always operate under a tail-agnostic policy 297 outCmpWithTail(i) := 1.U 298 }.otherwise { 299 outCmpWithTail(i) := outCmp(i) 300 } 301 } 302 303 /* insts whose mask is not used to generate 'agnosticEn' and 'activeEn' in mgu: 304 * vadc, vmadc... 305 * vmerge 306 */ 307 private val needNoMask = VialuFixType.needNoMask(outCtrl.fuOpType) 308 private val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask) 309 310 private val outFormat = VialuFixType.getFormat(outCtrl.fuOpType) 311 private val outWiden = (outFormat === VialuFixType.FMT.VVW | outFormat === VialuFixType.FMT.WVW) & !outVecCtrl.isExt & !outVecCtrl.isDstMask 312 private val narrow = outVecCtrl.isNarrow 313 private val dstMask = outVecCtrl.isDstMask 314 private val outVxsat = Mux(narrow, Cat(vIntFixpAlus.reverse.map(_.io.vxsat(3, 0))), Cat(vIntFixpAlus.reverse.map(_.io.vxsat))) 315 316 // the result of narrow inst which needs concat 317 private val narrowNeedCat = outVecCtrl.vuopIdx(0).asBool && narrow 318 private val outNarrowVd = Mux(narrowNeedCat, Cat(outNarrow, outOldVd(dataWidth / 2 - 1, 0)), Cat(outOldVd(dataWidth - 1, dataWidth / 2), outNarrow)) 319 private val outVxsatReal = Mux(narrowNeedCat, Cat(outVxsat(numBytes / 2 - 1, 0), 0.U((numBytes / 2).W)), outVxsat) 320 321 private val outEew = Mux(outWiden, outVecCtrl.vsew + 1.U, outVecCtrl.vsew) 322 323 /* 324 * vl of vmv.x.s is 1 325 */ 326 private val outIsVmvsx = outOpcode.isVmvsx 327 328 /* 329 * when vstart >= vl, no need to update vd, the old value should be kept 330 */ 331 private val outVstartGeVl = outVstart >= outVl 332 333 mgu.io.in.vd := MuxCase(outVd, Seq( 334 narrow -> outNarrowVd, 335 dstMask -> outCmpWithTail.asUInt, 336 )) 337 mgu.io.in.oldVd := outOldVd 338 mgu.io.in.mask := maskToMgu 339 mgu.io.in.info.ta := outVecCtrl.vta 340 mgu.io.in.info.ma := outVecCtrl.vma 341 mgu.io.in.info.vl := Mux(outIsVmvsx, 1.U, outVl) 342 mgu.io.in.info.vlmul := outVecCtrl.vlmul 343 mgu.io.in.info.valid := validVec.last 344 mgu.io.in.info.vstart := outVecCtrl.vstart 345 mgu.io.in.info.eew := outEew 346 mgu.io.in.info.vsew := outVecCtrl.vsew 347 mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx 348 mgu.io.in.info.narrow := narrow 349 mgu.io.in.info.dstMask := dstMask 350 mgu.io.in.isIndexedVls := false.B 351 352 /** 353 * [[mgtu]]'s in connection, for vmask instructions 354 */ 355 mgtu.io.in.vd := Mux(dstMask && !outVecCtrl.isOpMask, mgu.io.out.vd, outVd) 356 mgtu.io.in.vl := outVl 357 358 io.out.bits.res.data := Mux(outVstartGeVl, outOldVd, Mux(dstMask, mgtu.io.out.vd, mgu.io.out.vd)) 359 io.out.bits.res.vxsat.get := Mux(outVstartGeVl, false.B, (outVxsatReal & mgu.io.out.active).orR) 360 io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal && !outVstartGeVl 361 362 // util function 363 def splitMask(maskIn: UInt, sew: SewOH): Vec[UInt] = { 364 val maskWidth = maskIn.getWidth 365 val result = Wire(Vec(maskWidth / 8, UInt(8.W))) 366 for ((resultData, i) <- result.zipWithIndex) { 367 resultData := Mux1H(Seq( 368 sew.is8 -> maskIn(i * 8 + 7, i * 8), 369 sew.is16 -> Cat(0.U((8 - 4).W), maskIn(i * 4 + 3, i * 4)), 370 sew.is32 -> Cat(0.U((8 - 2).W), maskIn(i * 2 + 1, i * 2)), 371 sew.is64 -> Cat(0.U((8 - 1).W), maskIn(i)), 372 )) 373 } 374 result 375 } 376 377}