1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne, XSPerfAccumulate, XSPerfHistogram} 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.issue.EntryBundles._ 11import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 12import xiangshan.backend.datapath.DataConfig._ 13import xiangshan.backend.datapath.DataSource 14import xiangshan.backend.fu.{FuConfig, FuType} 15import xiangshan.backend.rob.RobPtr 16import xiangshan.backend.datapath.NewPipelineConnect 17import xiangshan.backend.fu.vector.Bundles.VSew 18import xiangshan.mem.{LqPtr, SqPtr} 19import xiangshan.mem.Bundles.MemWaitUpdateReqBundle 20import utility.PerfCCT 21 22class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 23 override def shouldBeInlined: Boolean = false 24 25 implicit val iqParams: IssueBlockParams = params 26 lazy val module: IssueQueueImp = iqParams.schdType match { 27 case IntScheduler() => new IssueQueueIntImp(this) 28 case FpScheduler() => new IssueQueueFpImp(this) 29 case VfScheduler() => new IssueQueueVfImp(this) 30 case MemScheduler() => 31 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 32 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 33 else new IssueQueueIntImp(this) 34 case _ => null 35 } 36} 37 38class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 39 val empty = Output(Bool()) 40 val full = Output(Bool()) 41 val validCnt = Output(UInt(log2Ceil(numEntries + 1).W)) 42 val leftVec = Output(Vec(numEnq + 1, Bool())) 43} 44 45class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 46 47class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 48 // Inputs 49 val flush = Flipped(ValidIO(new Redirect)) 50 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 51 52 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 53 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 54 val og2Resp = Option.when(params.needOg2Resp)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 55 val finalIssueResp = Option.when(params.LdExuCnt > 0 || params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 56 val memAddrIssueResp = Option.when(params.LdExuCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 57 val vecLoadIssueResp = Option.when(params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 58 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle) 59 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle) 60 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 61 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 62 val wakeupFromWBDelayed: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 63 val wakeupFromIQDelayed: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 64 val vlFromIntIsZero = Input(Bool()) 65 val vlFromIntIsVlmax = Input(Bool()) 66 val vlFromVfIsZero = Input(Bool()) 67 val vlFromVfIsVlmax = Input(Bool()) 68 val og0Cancel = Input(ExuVec()) 69 val og1Cancel = Input(ExuVec()) 70 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 71 val replaceRCIdx = Option.when(params.needWriteRegCache)(Vec(params.numDeq, Input(UInt(RegCacheIdxWidth.W)))) 72 73 // Outputs 74 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 75 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 76 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 77 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 78 79 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 80 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 81} 82 83class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 84 extends LazyModuleImp(wrapper) 85 with HasXSParameter { 86 87 override def desiredName: String = s"${params.getIQName}" 88 89 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 90 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 91 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 92 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 93 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 94 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 95 96 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 97 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 98 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 99 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 100 101 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 102 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 103 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 104 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 105 val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap) 106 107 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}") 108 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 109 if (params.hasIQWakeUp) { 110 val exuSourcesEncodeString = params.wakeUpSourceExuIdx.map(x => 1 << x).reduce(_ + _).toBinaryString 111 println(s"[IssueQueueImp] ${params.getIQName} exuSourcesWidth: ${ExuSource().value.getWidth}, " + 112 s"exuSourcesEncodeMask: ${"0" * (p(XSCoreParamsKey).backendParams.numExu - exuSourcesEncodeString.length) + exuSourcesEncodeString}") 113 } 114 115 lazy val io = IO(new IssueQueueIO()) 116 117 io.enq.zipWithIndex.foreach { case (enq, i) => 118 PerfCCT.updateInstPos(enq.bits.debug_seqNum, PerfCCT.InstPos.AtIssueQue.id.U, enq.valid, clock, reset) 119 } 120 121 // Modules 122 val entries = Module(new Entries) 123 val fuBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableWrite(x.fuLatencyMap))) } 124 val fuBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableRead(x.fuLatencyMap))) } 125 val intWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 126 val intWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableRead(x.intFuLatencyMap))) } 127 val fpWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableWrite(x.fpFuLatencyMap))) } 128 val fpWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableRead(x.fpFuLatencyMap))) } 129 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 130 val vfWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 131 val v0WbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableWrite(x.v0FuLatencyMap))) } 132 val v0WbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableRead(x.v0FuLatencyMap))) } 133 val vlWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableWrite(x.vlFuLatencyMap))) } 134 val vlWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableRead(x.vlFuLatencyMap))) } 135 136 class WakeupQueueFlush extends Bundle { 137 val redirect = ValidIO(new Redirect) 138 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 139 val og0Fail = Output(Bool()) 140 val og1Fail = Output(Bool()) 141 } 142 143 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 144 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 145 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 146 val ogFailFlush = stage match { 147 case 1 => flush.og0Fail 148 case 2 => flush.og1Fail 149 case _ => false.B 150 } 151 redirectFlush || loadDependencyFlush || ogFailFlush 152 } 153 154 private def modificationFunc(exuInput: ExuInput): ExuInput = { 155 val newExuInput = WireDefault(exuInput) 156 newExuInput.loadDependency match { 157 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 158 case None => 159 } 160 newExuInput 161 } 162 163 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 164 val lastExuInput = WireDefault(exuInput) 165 val newExuInput = WireDefault(newInput) 166 newExuInput.elements.foreach { case (name, data) => 167 if (lastExuInput.elements.contains(name)) { 168 data := lastExuInput.elements(name) 169 } 170 } 171 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 172 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 173 } 174 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 175 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 176 } 177 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 178 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 179 } 180 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 181 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.vecWen.get) 182 } 183 if (newExuInput.v0WenCopy.nonEmpty && !lastExuInput.v0WenCopy.nonEmpty) { 184 newExuInput.v0WenCopy.get.foreach(_ := lastExuInput.v0Wen.get) 185 } 186 if (newExuInput.vlWenCopy.nonEmpty && !lastExuInput.vlWenCopy.nonEmpty) { 187 newExuInput.vlWenCopy.get.foreach(_ := lastExuInput.vlWen.get) 188 } 189 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 190 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 191 } 192 newExuInput 193 } 194 195 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => Option.when(x.isIQWakeUpSource && !x.hasLoadExu)(Module( 196 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 197 ))} 198 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 199 200 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 201 val fpWbBusyTableIn = io.wbBusyTableRead.map(_.fpWbBusyTable) 202 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 203 val v0WbBusyTableIn = io.wbBusyTableRead.map(_.v0WbBusyTable) 204 val vlWbBusyTableIn = io.wbBusyTableRead.map(_.vlWbBusyTable) 205 206 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 207 val fpWbBusyTableOut = io.wbBusyTableWrite.map(_.fpWbBusyTable) 208 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 209 val v0WbBusyTableOut = io.wbBusyTableWrite.map(_.v0WbBusyTable) 210 val vlWbBusyTableOut = io.wbBusyTableWrite.map(_.vlWbBusyTable) 211 212 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 213 val fpDeqRespSetOut = io.wbBusyTableWrite.map(_.fpDeqRespSet) 214 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 215 val v0DeqRespSetOut = io.wbBusyTableWrite.map(_.v0DeqRespSet) 216 val vlDeqRespSetOut = io.wbBusyTableWrite.map(_.vlDeqRespSet) 217 218 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 219 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 220 val fpWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 221 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 222 val v0WbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 223 val vlWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 224 225 val s0_enqValidVec = io.enq.map(_.valid) 226 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 227 val s0_enqNotFlush = !io.flush.valid 228 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 229 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 230 231 232 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 233 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 234 235 val validVec = VecInit(entries.io.valid.asBools) 236 val issuedVec = VecInit(entries.io.issued.asBools) 237 val requestForTrans = VecInit(validVec.zip(issuedVec).map(x => x._1 && !x._2)) 238 val canIssueVec = VecInit(entries.io.canIssue.asBools) 239 dontTouch(canIssueVec) 240 val deqFirstIssueVec = entries.io.isFirstIssue 241 242 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 243 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 244 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 245 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 246 // (entryIdx)(srcIdx) 247 val exuSources: Option[Vec[Vec[ExuSource]]] = entries.io.exuSources 248 // (deqIdx)(srcIdx) 249 val finalExuSources: Option[Vec[Vec[ExuSource]]] = exuSources.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 250 251 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 252 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 253 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 254 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 255 256 //deq 257 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 258 val simpEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 259 val compEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 260 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 261 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 262 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 263 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 264 265 val subDeqSelValidVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, Bool()))) 266 val subDeqSelOHVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 267 val subDeqRequest = Option.when(params.deqFuSame)(Wire(UInt(params.numEntries.W))) 268 269 //trans 270 val simpEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 271 val compEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 272 val othersEntryEnqSelVec = Option.when(params.isAllComp || params.isAllSimp)(Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 273 val simpAgeDetectRequest = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 274 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 275 276 // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle 277 // as vf exu's min latency is 1, we do not need consider og0cancel 278 val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ)) 279 wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) => 280 if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) { 281 val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel) 282 w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w))) 283 w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) } 284 } else { 285 w := w_src 286 } 287 } 288 val wakeupFromIQDelayed = Wire(chiselTypeOf(io.wakeupFromIQDelayed)) 289 wakeupFromIQDelayed.zip(io.wakeupFromIQDelayed).foreach { case (w, w_src) => 290 if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) { 291 val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel) 292 w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w))) 293 w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach { case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) } 294 } else { 295 w := w_src 296 } 297 } 298 299 /** 300 * Connection of [[entries]] 301 */ 302 entries.io match { case entriesIO: EntriesIO => 303 entriesIO.flush := io.flush 304 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 305 enq.valid := s0_doEnqSelValidVec(enqIdx) 306 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 307 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 308 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 309 for(j <- 0 until numLsrc) { 310 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 311 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 312 enq.bits.status.srcStatus(j).srcState := (if (j < 3) { 313 Mux(SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 314 SrcState.rdy, 315 s0_enqBits(enqIdx).srcState(j)) 316 } else { 317 s0_enqBits(enqIdx).srcState(j) 318 }) 319 enq.bits.status.srcStatus(j).dataSources.value := (if (j < 3) { 320 MuxCase(DataSource.reg, Seq( 321 (SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.zero, 322 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 323 (SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.v0, 324 )) 325 } else { 326 MuxCase(DataSource.reg, Seq( 327 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 328 )) 329 }) 330 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x << 1)) 331 enq.bits.status.srcStatus(j).exuSources.foreach(_ := 0.U.asTypeOf(ExuSource())) 332 enq.bits.status.srcStatus(j).useRegCache.foreach(_ := s0_enqBits(enqIdx).useRegCache(j)) 333 enq.bits.status.srcStatus(j).regCacheIdx.foreach(_ := s0_enqBits(enqIdx).regCacheIdx(j)) 334 } 335 enq.bits.status.blocked := false.B 336 enq.bits.status.issued := false.B 337 enq.bits.status.firstIssue := false.B 338 enq.bits.status.issueTimer := "b11".U 339 enq.bits.status.deqPortIdx := 0.U 340 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 341 enq.bits.payload := s0_enqBits(enqIdx) 342 } 343 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 344 og0Resp := io.og0Resp(i) 345 } 346 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 347 og1Resp := io.og1Resp(i) 348 } 349 if (params.needOg2Resp) { 350 entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) => 351 og2Resp := io.og2Resp.get(i) 352 } 353 } 354 if (params.isLdAddrIQ || params.isHyAddrIQ) { 355 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 356 finalIssueResp := io.finalIssueResp.get(i) 357 } 358 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 359 memAddrIssueResp := io.memAddrIssueResp.get(i) 360 } 361 } 362 if (params.isVecLduIQ) { 363 entriesIO.vecLdIn.get.finalIssueResp.zipWithIndex.foreach { case (resp, i) => 364 resp := io.finalIssueResp.get(i) 365 } 366 entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) => 367 resp := io.vecLoadIssueResp.get(i) 368 } 369 } 370 for(deqIdx <- 0 until params.numDeq) { 371 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 372 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 373 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 374 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 375 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 376 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 377 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 378 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 379 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 380 } 381 entriesIO.wakeUpFromWB := io.wakeupFromWB 382 entriesIO.wakeUpFromIQ := wakeupFromIQ 383 entriesIO.wakeUpFromWBDelayed := io.wakeupFromWBDelayed 384 entriesIO.wakeUpFromIQDelayed := wakeupFromIQDelayed 385 entriesIO.vlFromIntIsZero := io.vlFromIntIsZero 386 entriesIO.vlFromIntIsVlmax := io.vlFromIntIsVlmax 387 entriesIO.vlFromVfIsZero := io.vlFromVfIsZero 388 entriesIO.vlFromVfIsVlmax := io.vlFromVfIsVlmax 389 entriesIO.og0Cancel := io.og0Cancel 390 entriesIO.og1Cancel := io.og1Cancel 391 entriesIO.ldCancel := io.ldCancel 392 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 393 //output 394 fuTypeVec := entriesIO.fuType 395 deqEntryVec := entriesIO.deqEntry 396 cancelDeqVec := entriesIO.cancelDeqVec 397 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 398 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 399 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 400 } 401 402 403 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 404 405 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 406 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 407 ).reverse) 408 409 // if deq port can accept the uop 410 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 411 Cat(fuTypeVec.map(fuType => 412 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 413 ).reverse) 414 } 415 416 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 417 fuTypeVec.map(fuType => 418 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 419 } 420 421 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 422 val mergeFuBusy = { 423 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 424 else canIssueVec.asUInt 425 } 426 val mergeIntWbBusy = { 427 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 428 else mergeFuBusy 429 } 430 val mergefpWbBusy = { 431 if (fpWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~fpWbBusyTableMask(i)) 432 else mergeIntWbBusy 433 } 434 val mergeVfWbBusy = { 435 if (vfWbBusyTableRead(i).nonEmpty) mergefpWbBusy & (~vfWbBusyTableMask(i)) 436 else mergefpWbBusy 437 } 438 val mergeV0WbBusy = { 439 if (v0WbBusyTableRead(i).nonEmpty) mergeVfWbBusy & (~v0WbBusyTableMask(i)) 440 else mergeVfWbBusy 441 } 442 val mergeVlWbBusy = { 443 if (vlWbBusyTableRead(i).nonEmpty) mergeV0WbBusy & (~vlWbBusyTableMask(i)) 444 else mergeV0WbBusy 445 } 446 merge := mergeVlWbBusy 447 } 448 449 deqCanIssue.zipWithIndex.foreach { case (req, i) => 450 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 451 } 452 dontTouch(fuTypeVec) 453 dontTouch(canIssueMergeAllBusy) 454 dontTouch(deqCanIssue) 455 456 if (params.numDeq == 2) { 457 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 458 } 459 460 if (params.numDeq == 2 && params.deqFuSame) { 461 val subDeqPolicy = Module(new DeqPolicy()) 462 463 enqEntryOldestSel := DontCare 464 465 if (params.isAllComp || params.isAllSimp) { 466 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 467 enq = othersEntryEnqSelVec.get, 468 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 469 ) 470 othersEntryOldestSel(1) := DontCare 471 472 subDeqPolicy.io.request := subDeqRequest.get 473 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 474 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 475 } 476 else { 477 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 478 simpAgeDetectRequest.get(1) := DontCare 479 simpAgeDetectRequest.get(params.numDeq) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt 480 if (params.numEnq == 2) { 481 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 482 } 483 484 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 485 enq = simpEntryEnqSelVec.get, 486 canIssue = simpAgeDetectRequest.get 487 ) 488 489 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 490 enq = compEntryEnqSelVec.get, 491 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 492 ) 493 compEntryOldestSel.get(1) := DontCare 494 495 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 496 othersEntryOldestSel(0).bits := Cat( 497 compEntryOldestSel.get(0).bits, 498 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 499 ) 500 othersEntryOldestSel(1) := DontCare 501 502 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 503 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 504 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 505 } 506 507 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 508 509 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 510 deqSelValidVec(1) := subDeqSelValidVec.get(0) 511 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 512 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 513 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 514 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 515 516 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 517 selValid := deqValid && deqOH.orR 518 selOH := deqOH 519 } 520 } 521 else { 522 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 523 enq = VecInit(s0_doEnqSelValidVec), 524 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 525 ) 526 527 if (params.isAllComp || params.isAllSimp) { 528 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 529 enq = othersEntryEnqSelVec.get, 530 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 531 ) 532 533 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 534 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 535 selValid := false.B 536 selOH := 0.U.asTypeOf(selOH) 537 } else { 538 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 539 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 540 } 541 } 542 } 543 else { 544 othersEntryOldestSel := DontCare 545 546 deqCanIssue.zipWithIndex.foreach { case (req, i) => 547 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 548 } 549 simpAgeDetectRequest.get(params.numDeq) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt 550 if (params.numEnq == 2) { 551 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 552 } 553 554 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 555 enq = simpEntryEnqSelVec.get, 556 canIssue = simpAgeDetectRequest.get 557 ) 558 559 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 560 enq = compEntryEnqSelVec.get, 561 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 562 ) 563 564 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 565 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 566 selValid := false.B 567 selOH := 0.U.asTypeOf(selOH) 568 } else { 569 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 570 selOH := Cat( 571 compEntryOldestSel.get(i).bits, 572 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 573 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 574 ) 575 } 576 } 577 } 578 579 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 580 selValid := deqValid 581 selOH := deqOH 582 } 583 } 584 585 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 586 587 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 588 deqResp.valid := deqBeforeDly(i).valid 589 deqResp.bits.resp := RespType.success 590 deqResp.bits.robIdx := DontCare 591 deqResp.bits.sqIdx.foreach(_ := DontCare) 592 deqResp.bits.lqIdx.foreach(_ := DontCare) 593 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 594 deqResp.bits.uopIdx.foreach(_ := DontCare) 595 } 596 597 //fuBusyTable 598 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 599 if(busyTableWrite.nonEmpty) { 600 val btwr = busyTableWrite.get 601 val btrd = busyTableRead.get 602 btwr.io.in.deqResp := toBusyTableDeqResp(i) 603 btwr.io.in.og0Resp := io.og0Resp(i) 604 btwr.io.in.og1Resp := io.og1Resp(i) 605 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 606 btrd.io.in.fuTypeRegVec := fuTypeVec 607 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 608 } 609 else { 610 fuBusyTableMask(i) := 0.U(params.numEntries.W) 611 } 612 } 613 614 //wbfuBusyTable write 615 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 616 if(busyTableWrite.nonEmpty) { 617 val btwr = busyTableWrite.get 618 val bt = busyTable.get 619 val dq = deqResp.get 620 btwr.io.in.deqResp := toBusyTableDeqResp(i) 621 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.rfWen.getOrElse(false.B) 622 btwr.io.in.og0Resp := io.og0Resp(i) 623 btwr.io.in.og1Resp := io.og1Resp(i) 624 bt := btwr.io.out.fuBusyTable 625 dq := btwr.io.out.deqRespSet 626 } 627 } 628 629 fpWbBusyTableWrite.zip(fpWbBusyTableOut).zip(fpDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 630 if (busyTableWrite.nonEmpty) { 631 val btwr = busyTableWrite.get 632 val bt = busyTable.get 633 val dq = deqResp.get 634 btwr.io.in.deqResp := toBusyTableDeqResp(i) 635 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.fpWen.getOrElse(false.B) 636 btwr.io.in.og0Resp := io.og0Resp(i) 637 btwr.io.in.og1Resp := io.og1Resp(i) 638 bt := btwr.io.out.fuBusyTable 639 dq := btwr.io.out.deqRespSet 640 } 641 } 642 643 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 644 if (busyTableWrite.nonEmpty) { 645 val btwr = busyTableWrite.get 646 val bt = busyTable.get 647 val dq = deqResp.get 648 btwr.io.in.deqResp := toBusyTableDeqResp(i) 649 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.vecWen.getOrElse(false.B) 650 btwr.io.in.og0Resp := io.og0Resp(i) 651 btwr.io.in.og1Resp := io.og1Resp(i) 652 bt := btwr.io.out.fuBusyTable 653 dq := btwr.io.out.deqRespSet 654 } 655 } 656 657 v0WbBusyTableWrite.zip(v0WbBusyTableOut).zip(v0DeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 658 if (busyTableWrite.nonEmpty) { 659 val btwr = busyTableWrite.get 660 val bt = busyTable.get 661 val dq = deqResp.get 662 btwr.io.in.deqResp := toBusyTableDeqResp(i) 663 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.v0Wen.getOrElse(false.B) 664 btwr.io.in.og0Resp := io.og0Resp(i) 665 btwr.io.in.og1Resp := io.og1Resp(i) 666 bt := btwr.io.out.fuBusyTable 667 dq := btwr.io.out.deqRespSet 668 } 669 } 670 671 vlWbBusyTableWrite.zip(vlWbBusyTableOut).zip(vlDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 672 if (busyTableWrite.nonEmpty) { 673 val btwr = busyTableWrite.get 674 val bt = busyTable.get 675 val dq = deqResp.get 676 btwr.io.in.deqResp := toBusyTableDeqResp(i) 677 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.vlWen.getOrElse(false.B) 678 btwr.io.in.og0Resp := io.og0Resp(i) 679 btwr.io.in.og1Resp := io.og1Resp(i) 680 bt := btwr.io.out.fuBusyTable 681 dq := btwr.io.out.deqRespSet 682 } 683 } 684 685 //wbfuBusyTable read 686 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 687 if(busyTableRead.nonEmpty) { 688 val btrd = busyTableRead.get 689 val bt = busyTable.get 690 btrd.io.in.fuBusyTable := bt 691 btrd.io.in.fuTypeRegVec := fuTypeVec 692 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 693 } 694 else { 695 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 696 } 697 } 698 fpWbBusyTableRead.zip(fpWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 699 if (busyTableRead.nonEmpty) { 700 val btrd = busyTableRead.get 701 val bt = busyTable.get 702 btrd.io.in.fuBusyTable := bt 703 btrd.io.in.fuTypeRegVec := fuTypeVec 704 fpWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 705 } 706 else { 707 fpWbBusyTableMask(i) := 0.U(params.numEntries.W) 708 } 709 } 710 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 711 if (busyTableRead.nonEmpty) { 712 val btrd = busyTableRead.get 713 val bt = busyTable.get 714 btrd.io.in.fuBusyTable := bt 715 btrd.io.in.fuTypeRegVec := fuTypeVec 716 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 717 } 718 else { 719 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 720 } 721 } 722 v0WbBusyTableRead.zip(v0WbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 723 if (busyTableRead.nonEmpty) { 724 val btrd = busyTableRead.get 725 val bt = busyTable.get 726 btrd.io.in.fuBusyTable := bt 727 btrd.io.in.fuTypeRegVec := fuTypeVec 728 v0WbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 729 } 730 else { 731 v0WbBusyTableMask(i) := 0.U(params.numEntries.W) 732 } 733 } 734 vlWbBusyTableRead.zip(vlWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 735 if (busyTableRead.nonEmpty) { 736 val btrd = busyTableRead.get 737 val bt = busyTable.get 738 btrd.io.in.fuBusyTable := bt 739 btrd.io.in.fuTypeRegVec := fuTypeVec 740 vlWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 741 } 742 else { 743 vlWbBusyTableMask(i) := 0.U(params.numEntries.W) 744 } 745 } 746 747 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 748 wakeUpQueueOption.foreach { 749 wakeUpQueue => 750 val flush = Wire(new WakeupQueueFlush) 751 flush.redirect := io.flush 752 flush.ldCancel := io.ldCancel 753 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 754 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 755 wakeUpQueue.io.flush := flush 756 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 757 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 758 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 759 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 760 } 761 } 762 763 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 764 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 765 deq.bits.addrOH := finalDeqSelOHVec(i) 766 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 767 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 768 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 769 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 770 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 771 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 772 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 773 deq.bits.common.v0Wen.foreach(_ := deqEntryVec(i).bits.payload.v0Wen) 774 deq.bits.common.vlWen.foreach(_ := deqEntryVec(i).bits.payload.vlWen) 775 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 776 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 777 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 778 779 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 780 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 781 deq.bits.common.exuSources.foreach(_.zip(finalExuSources.get(i)).foreach { case (sink, source) => sink := source}) 782 deq.bits.common.srcTimer.foreach(_ := DontCare) 783 deq.bits.common.loadDependency.foreach(_.zip(finalLoadDependency(i)).foreach { case (sink, source) => sink := source}) 784 deq.bits.common.src := DontCare 785 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 786 787 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 788 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 789 rf.foreach(_.addr := psrc) 790 rf.foreach(_.srcType := srcType) 791 } 792 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 793 sink := source 794 } 795 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 796 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 797 deq.bits.common.nextPcOffset.foreach(_ := 0.U) 798 deq.bits.rcIdx.foreach(_ := deqEntryVec(i).bits.status.srcStatus.map(_.regCacheIdx.get)) 799 800 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 801 deq.bits.common.perfDebugInfo.selectTime := GTimer() 802 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 803 deq.bits.common.debug_seqNum := deqEntryVec(i).bits.payload.debug_seqNum 804 } 805 806 val deqDelay = Reg(params.genIssueValidBundle) 807 deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) => 808 deqDly.valid := deq.valid 809 when(validVec.asUInt.orR) { 810 deqDly.bits := deq.bits 811 } 812 // deqBeforeDly.ready is always true 813 deq.ready := true.B 814 } 815 io.deqDelay.zip(deqDelay).foreach { case (sink, source) => 816 sink.valid := source.valid 817 sink.bits := source.bits 818 } 819 if(backendParams.debugEn) { 820 dontTouch(deqDelay) 821 dontTouch(io.deqDelay) 822 dontTouch(deqBeforeDly) 823 } 824 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 825 if (wakeUpQueues(i).nonEmpty) { 826 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 827 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 828 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 829 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 830 wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i)) 831 } else { 832 wakeup.valid := false.B 833 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 834 } 835 if (wakeUpQueues(i).nonEmpty) { 836 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 837 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 838 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 839 wakeup.bits.v0Wen := (if (wakeUpQueues(i).get.io.deq.bits.v0Wen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.v0Wen.get else false.B) 840 wakeup.bits.vlWen := (if (wakeUpQueues(i).get.io.deq.bits.vlWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vlWen.get else false.B) 841 } 842 843 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 844 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 845 } 846 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 847 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 848 } 849 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 850 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 851 } 852 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 853 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 854 } 855 if (wakeUpQueues(i).nonEmpty && wakeup.bits.v0WenCopy.nonEmpty) { 856 wakeup.bits.v0WenCopy.get := wakeUpQueues(i).get.io.deq.bits.v0WenCopy.get 857 } 858 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vlWenCopy.nonEmpty) { 859 wakeup.bits.vlWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vlWenCopy.get 860 } 861 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 862 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 863 } 864 } 865 866 // Todo: better counter implementation 867 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 868 private val enqHasIssued = validVec.zip(issuedVec).take(params.numEnq).map(x => x._1 & x._2).reduce(_ | _) 869 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 870 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 871 private val enqEntryValidCntDeq0 = PopCount( 872 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 873 ) 874 private val othersValidCntDeq0 = PopCount( 875 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 876 ) 877 private val enqEntryValidCntDeq1 = PopCount( 878 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 879 ) 880 private val othersValidCntDeq1 = PopCount( 881 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 882 ) 883 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 884 io.enq.map(_.bits.fuType).map(fuType => 885 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 886 } 887 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 888 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 889 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 890 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 891 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 892 for (i <- 0 until params.numEnq) { 893 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 894 } 895 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 896 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 897 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 898 } 899 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 900 private val othersCanotIn = Wire(Bool()) 901 othersCanotIn := othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 902 // if has simp Entry, othersCanotIn will be simpCanotIn 903 if (params.numSimp > 0) { 904 val simpLeftOneCaseVec = Wire(Vec(params.numSimp, UInt((params.numSimp).W))) 905 simpLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 906 leftone := ~(1.U((params.numSimp).W) << i) 907 } 908 val simpLeftOne = simpLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt).reduce(_ | _) 909 val simpCanotIn = simpLeftOne || validVec.drop(params.numEnq).take(params.numSimp).reduce(_ & _) 910 othersCanotIn := simpCanotIn 911 } 912 io.enq.foreach(_.ready := (!othersCanotIn || !enqHasValid) && !enqHasIssued) 913 io.status.empty := !Cat(validVec).orR 914 io.status.full := othersCanotIn 915 io.status.validCnt := PopCount(validVec) 916 917 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 918 Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 919 } 920 921 // issue perf counter 922 // enq count 923 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 924 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 925 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 926 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 927 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 928 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 929 // valid count 930 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 931 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 932 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 933 // only split when more than 1 func type 934 if (params.getFuCfgs.size > 0) { 935 for (t <- FuType.functionNameMap.keys) { 936 val fuName = FuType.functionNameMap(t) 937 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 938 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 939 } 940 } 941 } 942 // ready instr count 943 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 944 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 945 // only split when more than 1 func type 946 if (params.getFuCfgs.size > 0) { 947 for (t <- FuType.functionNameMap.keys) { 948 val fuName = FuType.functionNameMap(t) 949 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 950 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 951 } 952 } 953 } 954 955 // deq instr count 956 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 957 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 958 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 959 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 960 961 // deq instr data source count 962 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 963 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 964 }.reduce(_ +& _)) 965 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 966 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 967 }.reduce(_ +& _)) 968 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 969 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 970 }.reduce(_ +& _)) 971 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 972 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 973 }.reduce(_ +& _)) 974 975 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 976 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 977 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 978 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 979 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 980 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 981 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 982 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 983 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 984 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 985 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 986 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 987 988 // deq instr data source count for each futype 989 for (t <- FuType.functionNameMap.keys) { 990 val fuName = FuType.functionNameMap(t) 991 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 992 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 993 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 994 }.reduce(_ +& _)) 995 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 996 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 997 }.reduce(_ +& _)) 998 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 999 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 1000 }.reduce(_ +& _)) 1001 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 1002 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 1003 }.reduce(_ +& _)) 1004 1005 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 1006 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 1007 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 1008 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 1009 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 1010 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 1011 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 1012 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 1013 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 1014 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 1015 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 1016 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 1017 } 1018 } 1019} 1020 1021class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 1022 val fastMatch = UInt(backendParams.LduCnt.W) 1023 val fastImm = UInt(12.W) 1024} 1025 1026class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 1027 1028class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1029 extends IssueQueueImp(wrapper) 1030{ 1031 io.suggestName("none") 1032 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 1033 1034 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1035 deq.bits.common.pc.foreach(_ := DontCare) 1036 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 1037 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 1038 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 1039 deq.bits.common.predictInfo.foreach(x => { 1040 x.target := DontCare 1041 x.taken := deqEntryVec(i).bits.payload.pred_taken 1042 }) 1043 // for std 1044 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 1045 // for i2f 1046 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1047 }} 1048} 1049 1050class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1051 extends IssueQueueImp(wrapper) 1052{ 1053 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1054 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1055 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1056 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1057 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1058 }} 1059} 1060 1061class IssueQueueFpImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1062 extends IssueQueueImp(wrapper) 1063{ 1064 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1065 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1066 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1067 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1068 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1069 }} 1070} 1071 1072class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 1073 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ))) 1074 1075 // TODO: is still needed? 1076 val checkWait = new Bundle { 1077 val stIssuePtr = Input(new SqPtr) 1078 val memWaitUpdateReq = Flipped(new MemWaitUpdateReqBundle) 1079 } 1080 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 1081 1082 // load wakeup 1083 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 1084 1085 // vector 1086 val sqDeqPtr = Option.when(params.isVecMemIQ)(Input(new SqPtr)) 1087 val lqDeqPtr = Option.when(params.isVecMemIQ)(Input(new LqPtr)) 1088} 1089 1090class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 1091 val memIO = Some(new IssueQueueMemBundle) 1092} 1093 1094class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1095 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1096 1097 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 1098 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1099 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1100 1101 io.suggestName("none") 1102 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1103 private val memIO = io.memIO.get 1104 1105 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 1106 1107 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1108 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1109 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1110 slowResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx) 1111 slowResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx) 1112 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1113 slowResp.bits.fuType := DontCare 1114 } 1115 1116 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1117 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1118 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1119 fastResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.sqIdx) 1120 fastResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.lqIdx) 1121 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1122 fastResp.bits.fuType := DontCare 1123 } 1124 1125 // load wakeup 1126 val loadWakeUpIter = memIO.loadWakeUp.iterator 1127 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 1128 if (param.hasLoadExu) { 1129 require(wakeUpQueues(i).isEmpty) 1130 val uop = loadWakeUpIter.next() 1131 1132 wakeup.valid := GatedValidRegNext(uop.fire) 1133 wakeup.bits.rfWen := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B) 1134 wakeup.bits.fpWen := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B) 1135 wakeup.bits.vecWen := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B) 1136 wakeup.bits.v0Wen := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B) 1137 wakeup.bits.vlWen := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B) 1138 wakeup.bits.pdest := RegEnable(uop.bits.pdest, uop.fire) 1139 wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i)) 1140 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 1141 1142 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B))) 1143 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B))) 1144 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B))) 1145 wakeup.bits.v0WenCopy .foreach(_.foreach(_ := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B))) 1146 wakeup.bits.vlWenCopy .foreach(_.foreach(_ := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B))) 1147 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire))) 1148 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 1149 1150 wakeup.bits.is0Lat := 0.U 1151 } 1152 } 1153 require(!loadWakeUpIter.hasNext) 1154 1155 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1156 deq.bits.common.pc.foreach(_ := 0.U) 1157 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 1158 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 1159 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 1160 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 1161 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 1162 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 1163 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 1164 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 1165 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 1166 } 1167} 1168 1169class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1170 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1171 1172 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 1173 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 1174 1175 io.suggestName("none") 1176 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1177 private val memIO = io.memIO.get 1178 1179 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 1180 1181 for (i <- entries.io.enq.indices) { 1182 entries.io.enq(i).bits.status match { case enqData => 1183 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 1184 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 1185 // MemAddrIQ also handle vector insts 1186 enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem 1187 1188 val isFirstLoad = s0_enqBits(i).lqIdx <= memIO.lqDeqPtr.get 1189 val isVleff = s0_enqBits(i).vpu.isVleff 1190 enqData.blocked := !isFirstLoad && isVleff 1191 } 1192 } 1193 1194 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1195 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1196 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1197 slowResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx 1198 slowResp.bits.lqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx 1199 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1200 slowResp.bits.fuType := DontCare 1201 slowResp.bits.uopIdx.get := DontCare 1202 } 1203 1204 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1205 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1206 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1207 fastResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.sqIdx 1208 fastResp.bits.lqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.lqIdx 1209 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1210 fastResp.bits.fuType := DontCare 1211 fastResp.bits.uopIdx.get := DontCare 1212 } 1213 1214 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1215 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1216 1217 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1218 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1219 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1220 deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem) 1221 if (params.isVecLduIQ) { 1222 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1223 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1224 } 1225 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1226 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1227 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1228 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1229 } 1230 1231 io.vecLoadIssueResp.foreach(dontTouch(_)) 1232} 1233