xref: /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala (revision 2aaa83c0374a83bf896bf5106d9ce211df8ac6bb) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne}
8import utils._
9import xiangshan._
10import xiangshan.backend.Bundles._
11import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
12import xiangshan.backend.datapath.DataConfig._
13import xiangshan.backend.datapath.DataSource
14import xiangshan.backend.fu.{FuConfig, FuType}
15import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
16import xiangshan.backend.rob.RobPtr
17import xiangshan.backend.datapath.NewPipelineConnect
18
19class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
20  override def shouldBeInlined: Boolean = false
21
22  implicit val iqParams = params
23  lazy val module: IssueQueueImp = iqParams.schdType match {
24    case IntScheduler() => new IssueQueueIntImp(this)
25    case VfScheduler() => new IssueQueueVfImp(this)
26    case MemScheduler() =>
27      if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this)
28      else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this)
29      else new IssueQueueIntImp(this)
30    case _ => null
31  }
32}
33
34class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle {
35  val empty = Output(Bool())
36  val full = Output(Bool())
37  val validCnt = Output(UInt(log2Ceil(numEntries).W))
38  val leftVec = Output(Vec(numEnq + 1, Bool()))
39}
40
41class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle
42
43class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
44  // Inputs
45  val flush = Flipped(ValidIO(new Redirect))
46  val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst)))
47
48  val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
49  val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
50  val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
51  val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
52  val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle())
53  val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle())
54  val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
55  val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
56  val og0Cancel = Input(ExuOH(backendParams.numExu))
57  val og1Cancel = Input(ExuOH(backendParams.numExu))
58  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
59  val finalBlock = Vec(params.numExu, Input(Bool()))
60
61  // Outputs
62  val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle
63  val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries))
64  // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq))
65
66  val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType
67  def allWakeUp = wakeupFromWB ++ wakeupFromIQ
68}
69
70class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams)
71  extends LazyModuleImp(wrapper)
72  with HasXSParameter {
73
74  println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " +
75    s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " +
76    s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " +
77    s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}")
78
79  require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
80  val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
81  val allDeqFuCfgs  : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
82  val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
83  val commonFuCfgs  : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq
84  val fuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.fuLatencyMap)
85
86  println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${fuLatencyMaps}")
87  println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}")
88  lazy val io = IO(new IssueQueueIO())
89  // Modules
90
91  val entries = Module(new Entries)
92  val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) }
93  val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) }
94  val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) }
95  val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) }
96  val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) }
97  val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) }
98
99  class WakeupQueueFlush extends Bundle {
100    val redirect = ValidIO(new Redirect)
101    val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO)
102    val og0Fail = Output(Bool())
103    val og1Fail = Output(Bool())
104    val finalFail = Output(Bool())
105  }
106
107  private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = {
108    val redirectFlush = exuInput.robIdx.needFlush(flush.redirect)
109    val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel)
110    val ogFailFlush = stage match {
111      case 1 => flush.og0Fail
112      case 2 => flush.og1Fail
113      case 3 => flush.finalFail
114      case _ => false.B
115    }
116    redirectFlush || loadDependencyFlush || ogFailFlush
117  }
118
119  private def modificationFunc(exuInput: ExuInput): ExuInput = {
120    val newExuInput = WireDefault(exuInput)
121    newExuInput.loadDependency match {
122      case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1)
123      case None =>
124    }
125    newExuInput
126  }
127
128  private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = {
129    val lastExuInput = WireDefault(exuInput)
130    val newExuInput = WireDefault(newInput)
131    newExuInput.elements.foreach { case (name, data) =>
132      if (lastExuInput.elements.contains(name)) {
133        data := lastExuInput.elements(name)
134      }
135    }
136    if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) {
137      newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest)
138    }
139    if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) {
140      newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
141    }
142    if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) {
143      newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get)
144    }
145    if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) {
146      newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
147    }
148    if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) {
149      newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get)
150    }
151    newExuInput
152  }
153
154  val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource, Module(
155    new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.fuLatancySet, flushFunc, modificationFunc, lastConnectFunc)
156  ))}
157  val deqBeforeDly = Wire(params.genIssueDecoupledBundle)
158
159  val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable)
160  val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable)
161  val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable)
162  val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable)
163  val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet)
164  val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet)
165  val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
166  val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
167  val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
168  val s0_enqValidVec = io.enq.map(_.valid)
169  val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
170  val s0_enqNotFlush = !io.flush.valid
171  val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits)))
172  val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady
173
174
175  val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool()))
176  val finalDeqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
177
178  val validVec = VecInit(entries.io.valid.asBools)
179  val canIssueVec = VecInit(entries.io.canIssue.asBools)
180  val clearVec = VecInit(entries.io.clear.asBools)
181  val deqFirstIssueVec = VecInit(entries.io.deq.map(_.isFirstIssue))
182
183  val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources
184  val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources)))
185  // (entryIdx)(srcIdx)(exuIdx)
186  val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH
187  val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer
188
189  // (deqIdx)(srcIdx)(exuIdx)
190  val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
191  val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
192
193  val fuTypeVec = Wire(Vec(params.numEntries, FuType()))
194  val transEntryDeqVec = Wire(Vec(params.numEnq, ValidIO(new EntryBundle)))
195  val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))
196  val transSelVec = Wire(Vec(params.numEnq, UInt((params.numEntries-params.numEnq).W)))
197  val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
198  val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
199
200  val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W))))
201  val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W))))
202  val deqSelValidVec = Wire(Vec(params.numDeq, Bool()))
203  val deqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
204  val cancelDeqVec = Wire(Vec(params.numDeq, Bool()))
205
206  val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool())))
207  val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W))))
208  val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W)))
209
210  /**
211    * Connection of [[entries]]
212    */
213  entries.io match { case entriesIO: EntriesIO =>
214    entriesIO.flush <> io.flush
215    entriesIO.wakeUpFromWB := io.wakeupFromWB
216    entriesIO.wakeUpFromIQ := io.wakeupFromIQ
217    entriesIO.og0Cancel := io.og0Cancel
218    entriesIO.og1Cancel := io.og1Cancel
219    entriesIO.ldCancel := io.ldCancel
220    entriesIO.enq.zipWithIndex.foreach { case (enq: ValidIO[EntryBundle], i) =>
221      enq.valid := s0_doEnqSelValidVec(i)
222      val numLsrc = s0_enqBits(i).srcType.size.min(enq.bits.status.srcType.size)
223      for (j <- 0 until numLsrc) {
224        enq.bits.status.srcState(j) := s0_enqBits(i).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(i).srcLoadDependency(j)), io.ldCancel)
225        enq.bits.status.psrc(j) := s0_enqBits(i).psrc(j)
226        enq.bits.status.srcType(j) := s0_enqBits(i).srcType(j)
227        enq.bits.status.dataSources(j).value := DataSource.reg
228        enq.bits.payload.debugInfo.enqRsTime := GTimer()
229      }
230      enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(i).fuType.asBools), params.getFuCfgs.map(_.fuType))
231      enq.bits.status.robIdx := s0_enqBits(i).robIdx
232      enq.bits.status.uopIdx.foreach(_ := s0_enqBits(i).uopIdx)
233      enq.bits.status.issueTimer := "b10".U
234      enq.bits.status.deqPortIdx := 0.U
235      enq.bits.status.issued := false.B
236      enq.bits.status.firstIssue := false.B
237      enq.bits.status.blocked := false.B
238
239      if (params.hasIQWakeUp) {
240        enq.bits.status.srcWakeUpL1ExuOH.get := 0.U.asTypeOf(enq.bits.status.srcWakeUpL1ExuOH.get)
241        enq.bits.status.srcTimer.get := 0.U.asTypeOf(enq.bits.status.srcTimer.get)
242        enq.bits.status.srcLoadDependency.foreach(_.zipWithIndex.foreach {
243          case (dep, srcIdx) =>
244            dep := VecInit(s0_enqBits(i).srcLoadDependency(srcIdx).map(x => x(x.getWidth - 2, 0) << 1))
245        })
246      }
247      if (params.inIntSchd && params.AluCnt > 0) {
248        // dirty code for lui+addi(w) fusion
249        val isLuiAddiFusion = s0_enqBits(i).isLUI32
250        val luiImm = Cat(s0_enqBits(i).lsrc(1), s0_enqBits(i).lsrc(0), s0_enqBits(i).imm(ImmUnion.maxLen - 1, 0))
251        enq.bits.imm.foreach(_ := Mux(isLuiAddiFusion, ImmUnion.LUI32.toImm32(luiImm), s0_enqBits(i).imm))
252      }
253      else if (params.inMemSchd && params.LduCnt > 0) {
254        // dirty code for fused_lui_load
255        val isLuiLoadFusion = SrcType.isNotReg(s0_enqBits(i).srcType(0)) && FuType.isLoad(s0_enqBits(i).fuType)
256        enq.bits.imm.foreach(_ := Mux(isLuiLoadFusion, Imm_LUI_LOAD().getLuiImm(s0_enqBits(i)), s0_enqBits(i).imm))
257      }
258      else {
259        enq.bits.imm.foreach(_ := s0_enqBits(i).imm)
260      }
261      enq.bits.payload := s0_enqBits(i)
262    }
263    entriesIO.deq.zipWithIndex.foreach { case (deq, i) =>
264      deq.enqEntryOldestSel := enqEntryOldestSel(i)
265      deq.othersEntryOldestSel := othersEntryOldestSel(i)
266      deq.subDeqRequest.foreach(_ := subDeqRequest.get)
267      deq.subDeqSelOH.foreach(_ := subDeqSelOHVec.get(i))
268      deq.deqReady := deqBeforeDly(i).ready
269      deq.deqSelOH.valid := deqSelValidVec(i)
270      deq.deqSelOH.bits := deqSelOHVec(i)
271    }
272    entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) =>
273      og0Resp.valid := io.og0Resp(i).valid
274      og0Resp.bits.robIdx := io.og0Resp(i).bits.robIdx
275      og0Resp.bits.uopIdx := io.og0Resp(i).bits.uopIdx
276      og0Resp.bits.dataInvalidSqIdx := io.og0Resp(i).bits.dataInvalidSqIdx
277      og0Resp.bits.respType := io.og0Resp(i).bits.respType
278      og0Resp.bits.rfWen := io.og0Resp(i).bits.rfWen
279      og0Resp.bits.fuType := io.og0Resp(i).bits.fuType
280    }
281    entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) =>
282      og1Resp.valid := io.og1Resp(i).valid
283      og1Resp.bits.robIdx := io.og1Resp(i).bits.robIdx
284      og1Resp.bits.uopIdx := io.og1Resp(i).bits.uopIdx
285      og1Resp.bits.dataInvalidSqIdx := io.og1Resp(i).bits.dataInvalidSqIdx
286      og1Resp.bits.respType := io.og1Resp(i).bits.respType
287      og1Resp.bits.rfWen := io.og1Resp(i).bits.rfWen
288      og1Resp.bits.fuType := io.og1Resp(i).bits.fuType
289    }
290    entriesIO.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, i) =>
291      finalIssueResp := io.finalIssueResp.get(i)
292    })
293    entriesIO.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, i) =>
294      memAddrIssueResp := io.memAddrIssueResp.get(i)
295    })
296    transEntryDeqVec := entriesIO.transEntryDeqVec
297    deqEntryVec := entriesIO.deq.map(_.deqEntry)
298    fuTypeVec := entriesIO.fuType
299    cancelDeqVec := entriesIO.cancelDeqVec
300    transSelVec := entriesIO.transSelVec
301  }
302
303
304  s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready}
305
306  protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType =>
307    FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType))
308  ).reverse)
309
310  // if deq port can accept the uop
311  protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
312    Cat(fuTypeVec.map(fuType =>
313      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))
314    ).reverse)
315  }
316
317  protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
318    fuTypeVec.map(fuType =>
319      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
320  }
321
322  canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) =>
323    val mergeFuBusy = {
324      if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i))
325      else canIssueVec.asUInt
326    }
327    val mergeIntWbBusy = {
328      if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i))
329      else mergeFuBusy
330    }
331    val mergeVfWbBusy = {
332      if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i))
333      else mergeIntWbBusy
334    }
335    merge := mergeVfWbBusy
336  }
337
338  deqCanIssue.zipWithIndex.foreach { case (req, i) =>
339    req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt
340  }
341
342  if (params.numDeq == 2) {
343    require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different")
344  }
345
346  if (params.numDeq == 2 && params.deqFuSame) {
347    enqEntryOldestSel := DontCare
348
349    othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq,
350      enq = VecInit(transEntryDeqVec.zip(transSelVec).map{ case (transEntry, transSel) => Fill(params.numEntries-params.numEnq, transEntry.valid) & transSel }),
351      canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq)
352    )
353    othersEntryOldestSel(1) := DontCare
354
355    subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W))
356
357    val subDeqPolicy = Module(new DeqPolicy())
358    subDeqPolicy.io.request := subDeqRequest.get
359    subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
360    subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits)
361
362    deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1)
363    deqSelValidVec(1) := subDeqSelValidVec.get(0)
364    deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid,
365                          Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)),
366                          subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0)
367    deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1)
368
369    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
370      selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready
371      selOH := deqOH
372    }
373  }
374  else {
375    enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq,
376      enq = VecInit(s0_doEnqSelValidVec),
377      canIssue = VecInit(deqCanIssue.map(_(params.numEnq-1, 0)))
378    )
379
380    othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq,
381      enq = VecInit(transEntryDeqVec.zip(transSelVec).map{ case (transEntry, transSel) => Fill(params.numEntries-params.numEnq, transEntry.valid) & transSel }),
382      canIssue = VecInit(deqCanIssue.map(_(params.numEntries-1, params.numEnq)))
383    )
384
385    deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
386      if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
387        selValid := false.B
388        selOH := 0.U.asTypeOf(selOH)
389      } else {
390        selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid
391        selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, enqEntryOldestSel(i).valid && !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits)
392      }
393    }
394
395    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
396      selValid := deqValid && deqBeforeDly(i).ready
397      selOH := deqOH
398    }
399  }
400
401  val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle)))
402
403  toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) =>
404    deqResp.valid := finalDeqSelValidVec(i)
405    deqResp.bits.respType := RSFeedbackType.issueSuccess
406    deqResp.bits.robIdx := DontCare
407    deqResp.bits.dataInvalidSqIdx := DontCare
408    deqResp.bits.rfWen := DontCare
409    deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType
410    deqResp.bits.uopIdx := DontCare
411  }
412
413  //fuBusyTable
414  fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) =>
415    if(busyTableWrite.nonEmpty) {
416      val btwr = busyTableWrite.get
417      val btrd = busyTableRead.get
418      btwr.io.in.deqResp := toBusyTableDeqResp(i)
419      btwr.io.in.og0Resp := io.og0Resp(i)
420      btwr.io.in.og1Resp := io.og1Resp(i)
421      btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable
422      btrd.io.in.fuTypeRegVec := fuTypeVec
423      fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask
424    }
425    else {
426      fuBusyTableMask(i) := 0.U(params.numEntries.W)
427    }
428  }
429
430  //wbfuBusyTable write
431  intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
432    if(busyTableWrite.nonEmpty) {
433      val btwr = busyTableWrite.get
434      val bt = busyTable.get
435      val dq = deqResp.get
436      btwr.io.in.deqResp := toBusyTableDeqResp(i)
437      btwr.io.in.og0Resp := io.og0Resp(i)
438      btwr.io.in.og1Resp := io.og1Resp(i)
439      bt := btwr.io.out.fuBusyTable
440      dq := btwr.io.out.deqRespSet
441    }
442  }
443
444  vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
445    if (busyTableWrite.nonEmpty) {
446      val btwr = busyTableWrite.get
447      val bt = busyTable.get
448      val dq = deqResp.get
449      btwr.io.in.deqResp := toBusyTableDeqResp(i)
450      btwr.io.in.og0Resp := io.og0Resp(i)
451      btwr.io.in.og1Resp := io.og1Resp(i)
452      bt := btwr.io.out.fuBusyTable
453      dq := btwr.io.out.deqRespSet
454    }
455  }
456
457  //wbfuBusyTable read
458  intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
459    if(busyTableRead.nonEmpty) {
460      val btrd = busyTableRead.get
461      val bt = busyTable.get
462      btrd.io.in.fuBusyTable := bt
463      btrd.io.in.fuTypeRegVec := fuTypeVec
464      intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
465    }
466    else {
467      intWbBusyTableMask(i) := 0.U(params.numEntries.W)
468    }
469  }
470  vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
471    if (busyTableRead.nonEmpty) {
472      val btrd = busyTableRead.get
473      val bt = busyTable.get
474      btrd.io.in.fuBusyTable := bt
475      btrd.io.in.fuTypeRegVec := fuTypeVec
476      vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
477    }
478    else {
479      vfWbBusyTableMask(i) := 0.U(params.numEntries.W)
480    }
481  }
482
483  wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) =>
484    wakeUpQueueOption.foreach {
485      wakeUpQueue =>
486        val flush = Wire(new WakeupQueueFlush)
487        flush.redirect := io.flush
488        flush.ldCancel := io.ldCancel
489        flush.og0Fail := io.og0Resp(i).valid && RSFeedbackType.isBlocked(io.og0Resp(i).bits.respType)
490        flush.og1Fail := io.og1Resp(i).valid && RSFeedbackType.isBlocked(io.og1Resp(i).bits.respType)
491        flush.finalFail := io.finalBlock(i)
492        wakeUpQueue.io.flush := flush
493        wakeUpQueue.io.enq.valid := deqBeforeDly(i).fire
494        wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common
495        wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U)
496        wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType)
497    }
498  }
499
500  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
501    deq.valid                := finalDeqSelValidVec(i) && !cancelDeqVec(i)
502    deq.bits.addrOH          := finalDeqSelOHVec(i)
503    deq.bits.common.isFirstIssue := deqFirstIssueVec(i)
504    deq.bits.common.iqIdx    := OHToUInt(finalDeqSelOHVec(i))
505    deq.bits.common.fuType   := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt
506    deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType
507    deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen)
508    deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen)
509    deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen)
510    deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe)
511    deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest
512    deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx
513
514    require(deq.bits.common.dataSources.size <= finalDataSources(i).size)
515    deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source}
516    deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i))
517    deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i))
518    deq.bits.common.loadDependency.foreach(_ := deqEntryVec(i).bits.status.mergedLoadDependency.get)
519    deq.bits.common.deqLdExuIdx.foreach(_ := params.backendParam.getLdExuIdx(deq.bits.exuParams).U)
520    deq.bits.common.src := DontCare
521    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
522
523    deq.bits.rf.zip(deqEntryVec(i).bits.status.psrc).zip(deqEntryVec(i).bits.status.srcType).foreach { case ((rf, psrc), srcType) =>
524      // psrc in status array can be pregIdx of IntRegFile or VfRegFile
525      rf.foreach(_.addr := psrc)
526      rf.foreach(_.srcType := srcType)
527    }
528    deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcType).foreach { case (sink, source) =>
529      sink := source
530    }
531    deq.bits.immType := deqEntryVec(i).bits.payload.selImm
532    deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U)
533
534    deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo
535    deq.bits.common.perfDebugInfo.selectTime := GTimer()
536    deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U
537  }
538
539  private val deqShift = WireDefault(deqBeforeDly)
540  deqShift.zip(deqBeforeDly).foreach {
541    case (shifted, original) =>
542      original.ready := shifted.ready // this will not cause combinational loop
543      shifted.bits.common.loadDependency.foreach(
544        _ := original.bits.common.loadDependency.get.map(_ << 1)
545      )
546  }
547  io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) =>
548    NewPipelineConnect(
549      deq, deqDly, deqDly.valid,
550      false.B,
551      Option("Scheduler2DataPathPipe")
552    )
553  }
554  if(backendParams.debugEn) {
555    dontTouch(io.deqDelay)
556  }
557  io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) =>
558    if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) {
559      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
560      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i))
561      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
562      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
563    } else if (wakeUpQueues(i).nonEmpty) {
564      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
565      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits)
566      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
567      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
568    } else {
569      wakeup.valid := false.B
570      wakeup.bits := 0.U.asTypeOf(wakeup.bits)
571      wakeup.bits.is0Lat :=  0.U
572    }
573    if (wakeUpQueues(i).nonEmpty) {
574      wakeup.bits.rfWen  := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B)
575      wakeup.bits.fpWen  := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B)
576      wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B)
577    }
578
579    if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){
580      wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get
581    }
582    if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) {
583      wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get
584    }
585    if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) {
586      wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get
587    }
588    if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) {
589      wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get
590    }
591    if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) {
592      wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get
593    }
594  }
595
596  // Todo: better counter implementation
597  private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _)
598  private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq))
599  private val othersValidCnt = PopCount(validVec.drop(params.numEnq))
600  io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _)
601  for (i <- 0 until params.numEnq) {
602    io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U
603  }
604  private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W)))
605  othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) =>
606    leftone := ~(1.U((params.numEntries - params.numEnq).W) << i)
607  }
608  private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _)
609  private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _)
610
611  io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid)
612  io.status.empty := !Cat(validVec).orR
613  io.status.full := othersCanotIn
614  io.status.validCnt := PopCount(validVec)
615
616  protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = {
617    Mux1H(fuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) })
618  }
619
620  // issue perf counter
621  // enq count
622  XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire)))
623  XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire)))
624  // valid count
625  XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1)
626  XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1)
627  XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1)
628  // only split when more than 1 func type
629  if (params.getFuCfgs.size > 0) {
630    for (t <- FuType.functionNameMap.keys) {
631      val fuName = FuType.functionNameMap(t)
632      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
633        XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1)
634      }
635    }
636  }
637  // ready instr count
638  private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2))
639  XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1)
640  // only split when more than 1 func type
641  if (params.getFuCfgs.size > 0) {
642    for (t <- FuType.functionNameMap.keys) {
643      val fuName = FuType.functionNameMap(t)
644      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
645        XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1)
646      }
647    }
648  }
649
650  // deq instr count
651  XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid)))
652  XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
653  XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid)))
654  XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
655
656  // deq instr data source count
657  XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq =>
658    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
659  }.reduce(_ +& _))
660  XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq =>
661    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
662  }.reduce(_ +& _))
663  XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq =>
664    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
665  }.reduce(_ +& _))
666  XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq =>
667    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
668  }.reduce(_ +& _))
669
670  XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq =>
671    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
672  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
673  XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq =>
674    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
675  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
676  XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq =>
677    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
678  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
679  XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq =>
680    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
681  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
682
683  // deq instr data source count for each futype
684  for (t <- FuType.functionNameMap.keys) {
685    val fuName = FuType.functionNameMap(t)
686    if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
687      XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq =>
688        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
689      }.reduce(_ +& _))
690      XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq =>
691        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
692      }.reduce(_ +& _))
693      XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq =>
694        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
695      }.reduce(_ +& _))
696      XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq =>
697        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
698      }.reduce(_ +& _))
699
700      XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
701        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
702      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
703      XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
704        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
705      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
706      XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
707        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
708      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
709      XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
710        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
711      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
712    }
713  }
714
715  // cancel instr count
716  if (params.hasIQWakeUp) {
717    val cancelVec: Vec[Bool] = entries.io.cancel.get
718    XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)))
719    XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1)
720    for (t <- FuType.functionNameMap.keys) {
721      val fuName = FuType.functionNameMap(t)
722      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
723        XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }))
724        XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1)
725      }
726    }
727  }
728}
729
730class IssueQueueJumpBundle extends Bundle {
731  val pc = UInt(VAddrData().dataWidth.W)
732}
733
734class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle {
735  val fastMatch = UInt(backendParams.LduCnt.W)
736  val fastImm = UInt(12.W)
737}
738
739class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO
740
741class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
742  extends IssueQueueImp(wrapper)
743{
744  io.suggestName("none")
745  override lazy val io = IO(new IssueQueueIntIO).suggestName("io")
746
747  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
748    deq.bits.common.pc.foreach(_ := deqEntryVec(i).bits.payload.pc)
749    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
750    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
751    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
752    deq.bits.common.predictInfo.foreach(x => {
753      x.target := DontCare
754      x.taken := deqEntryVec(i).bits.payload.pred_taken
755    })
756    // for std
757    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
758    // for i2f
759    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
760  }}
761}
762
763class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
764  extends IssueQueueImp(wrapper)
765{
766  s0_enqBits.foreach{ x =>
767    x.srcType(3) := SrcType.vp // v0: mask src
768    x.srcType(4) := SrcType.vp // vl&vtype
769  }
770  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
771    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
772    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
773    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
774    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
775  }}
776}
777
778class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle {
779  val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO))
780  val checkWait = new Bundle {
781    val stIssuePtr = Input(new SqPtr)
782    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
783  }
784  val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle))
785
786  // vector
787  val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr))
788  val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr))
789}
790
791class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO {
792  val memIO = Some(new IssueQueueMemBundle)
793}
794
795class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
796  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
797
798  require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt + params.VlduCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " +
799    s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
800  println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
801
802  io.suggestName("none")
803  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
804  private val memIO = io.memIO.get
805
806  memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed?
807
808  for (i <- io.enq.indices) {
809    val blockNotReleased = isAfter(io.enq(i).bits.sqIdx, memIO.checkWait.stIssuePtr)
810    val storeAddrWaitForIsIssuing = VecInit((0 until StorePipelineWidth).map(i => {
811      memIO.checkWait.memWaitUpdateReq.robIdx(i).valid &&
812        memIO.checkWait.memWaitUpdateReq.robIdx(i).bits.value === io.enq(i).bits.waitForRobIdx.value
813    })).asUInt.orR && !io.enq(i).bits.loadWaitStrict // is waiting for store addr ready
814    s0_enqBits(i).loadWaitBit := io.enq(i).bits.loadWaitBit && !storeAddrWaitForIsIssuing && blockNotReleased
815    // when have vpu
816    if (params.VlduCnt > 0 || params.VstuCnt > 0) {
817      s0_enqBits(i).srcType(3) := SrcType.vp // v0: mask src
818      s0_enqBits(i).srcType(4) := SrcType.vp // vl&vtype
819    }
820  }
821
822  for (i <- entries.io.enq.indices) {
823    entries.io.enq(i).bits.status match { case enqData =>
824      enqData.blocked := false.B // s0_enqBits(i).loadWaitBit
825      enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict
826      enqData.mem.get.waitForStd := false.B
827      enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx
828      enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later
829      enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx
830    }
831
832    entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
833      slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
834      slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
835      slowResp.bits.uopIdx           := DontCare
836      slowResp.bits.respType         := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RSFeedbackType.fuIdle, RSFeedbackType.feedbackInvalid)
837      slowResp.bits.dataInvalidSqIdx := memIO.feedbackIO(i).feedbackSlow.bits.dataInvalidSqIdx
838      slowResp.bits.rfWen := DontCare
839      slowResp.bits.fuType := DontCare
840    }
841
842    entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
843      fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
844      fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
845      fastResp.bits.uopIdx           := DontCare
846      fastResp.bits.respType         := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RSFeedbackType.fuIdle, memIO.feedbackIO(i).feedbackFast.bits.sourceType)
847      fastResp.bits.dataInvalidSqIdx := 0.U.asTypeOf(fastResp.bits.dataInvalidSqIdx)
848      fastResp.bits.rfWen := DontCare
849      fastResp.bits.fuType := DontCare
850    }
851
852    entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq
853    entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr
854  }
855
856  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
857    deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit)
858    deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx)
859    deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit)
860    deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict)
861    deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid)
862    deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx
863    deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx
864    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
865    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
866    // when have vpu
867    if (params.VlduCnt > 0 || params.VstuCnt > 0) {
868      deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
869      deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
870    }
871  }
872}
873
874class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
875  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
876
877  require((params.VstdCnt + params.VlduCnt + params.VstaCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ")
878
879  io.suggestName("none")
880  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
881  private val memIO = io.memIO.get
882
883  def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = {
884    val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j))))
885    val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j =>
886      (if (j < i) !valid(j) || compareVec(i)(j)
887      else if (j == i) valid(i)
888      else !valid(j) || !compareVec(j)(i))
889    )).andR))
890    resultOnehot
891  }
892
893  val robIdxVec = entries.io.robIdx.get
894  val uopIdxVec = entries.io.uopIdx.get
895  val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec)
896
897  finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR
898  finalDeqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt
899
900  if (params.isVecMemAddrIQ) {
901    s0_enqBits.foreach{ x =>
902      x.srcType(3) := SrcType.vp // v0: mask src
903      x.srcType(4) := SrcType.vp // vl&vtype
904    }
905
906    for (i <- io.enq.indices) {
907      s0_enqBits(i).loadWaitBit := false.B
908    }
909
910    for (i <- entries.io.enq.indices) {
911      entries.io.enq(i).bits.status match { case enqData =>
912        enqData.blocked := false.B // s0_enqBits(i).loadWaitBit
913        enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict
914        enqData.mem.get.waitForStd := false.B
915        enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx
916        enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later
917        enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx
918      }
919
920      entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
921        slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
922        slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
923        slowResp.bits.uopIdx           := DontCare
924        slowResp.bits.respType         := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RSFeedbackType.fuIdle, RSFeedbackType.feedbackInvalid)
925        slowResp.bits.dataInvalidSqIdx := memIO.feedbackIO(i).feedbackSlow.bits.dataInvalidSqIdx
926        slowResp.bits.rfWen := DontCare
927        slowResp.bits.fuType := DontCare
928      }
929
930      entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
931        fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
932        fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
933        fastResp.bits.uopIdx           := DontCare
934        fastResp.bits.respType         := memIO.feedbackIO(i).feedbackFast.bits.sourceType
935        fastResp.bits.dataInvalidSqIdx := 0.U.asTypeOf(fastResp.bits.dataInvalidSqIdx)
936        fastResp.bits.rfWen := DontCare
937        fastResp.bits.fuType := DontCare
938      }
939
940      entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq
941      entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr
942    }
943  }
944
945  for (i <- entries.io.enq.indices) {
946    entries.io.enq(i).bits.status match { case enqData =>
947      enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx
948      enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx
949    }
950  }
951
952  entries.io.fromLsq.get.sqDeqPtr := memIO.sqDeqPtr.get
953  entries.io.fromLsq.get.lqDeqPtr := memIO.lqDeqPtr.get
954
955  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
956    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
957    deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.payload.lqIdx)
958    if (params.isVecLdAddrIQ) {
959      deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr
960      deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset
961    }
962    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
963    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
964    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
965    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
966  }
967}
968