xref: /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala (revision 4aa0028654716f3ef660f985eb6662c6c75b70d0) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne}
8import utils._
9import xiangshan._
10import xiangshan.backend.Bundles._
11import xiangshan.backend.issue.EntryBundles._
12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
13import xiangshan.backend.datapath.DataConfig._
14import xiangshan.backend.datapath.DataSource
15import xiangshan.backend.fu.{FuConfig, FuType}
16import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr}
17import xiangshan.backend.rob.RobPtr
18import xiangshan.backend.datapath.NewPipelineConnect
19import xiangshan.backend.fu.vector.Bundles.VSew
20
21class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
22  override def shouldBeInlined: Boolean = false
23
24  implicit val iqParams = params
25  lazy val module: IssueQueueImp = iqParams.schdType match {
26    case IntScheduler() => new IssueQueueIntImp(this)
27    case VfScheduler() => new IssueQueueVfImp(this)
28    case MemScheduler() =>
29      if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this)
30      else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this)
31      else new IssueQueueIntImp(this)
32    case _ => null
33  }
34}
35
36class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle {
37  val empty = Output(Bool())
38  val full = Output(Bool())
39  val validCnt = Output(UInt(log2Ceil(numEntries).W))
40  val leftVec = Output(Vec(numEnq + 1, Bool()))
41}
42
43class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle
44
45class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
46  // Inputs
47  val flush = Flipped(ValidIO(new Redirect))
48  val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst)))
49
50  val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
51  val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
52  val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
53  val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
54  val vecLoadIssueResp = OptionWrapper(params.VlduCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
55  val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle())
56  val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle())
57  val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
58  val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
59  val vlIsZero = Input(Bool())
60  val vlIsVlmax = Input(Bool())
61  val og0Cancel = Input(ExuOH(backendParams.numExu))
62  val og1Cancel = Input(ExuOH(backendParams.numExu))
63  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
64
65  // Outputs
66  val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle
67  val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries))
68  val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W)))
69  // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq))
70
71  val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType
72  def allWakeUp = wakeupFromWB ++ wakeupFromIQ
73}
74
75class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams)
76  extends LazyModuleImp(wrapper)
77  with HasXSParameter {
78
79  override def desiredName: String = s"${params.getIQName}"
80
81  println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " +
82    s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " +
83    s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " +
84    s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " +
85    s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " +
86    s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}")
87
88  require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
89  require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports")
90  require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq")
91  require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq")
92
93  val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
94  val allDeqFuCfgs  : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
95  val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
96  val commonFuCfgs  : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq
97  val fuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.fuLatencyMap)
98
99  println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${fuLatencyMaps}")
100  println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}")
101  lazy val io = IO(new IssueQueueIO())
102
103  // Modules
104  val entries = Module(new Entries)
105  val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) }
106  val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) }
107  val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) }
108  val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) }
109  val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) }
110  val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) }
111
112  class WakeupQueueFlush extends Bundle {
113    val redirect = ValidIO(new Redirect)
114    val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO)
115    val og0Fail = Output(Bool())
116    val og1Fail = Output(Bool())
117  }
118
119  private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = {
120    val redirectFlush = exuInput.robIdx.needFlush(flush.redirect)
121    val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel)
122    val ogFailFlush = stage match {
123      case 1 => flush.og0Fail
124      case 2 => flush.og1Fail
125      case _ => false.B
126    }
127    redirectFlush || loadDependencyFlush || ogFailFlush
128  }
129
130  private def modificationFunc(exuInput: ExuInput): ExuInput = {
131    val newExuInput = WireDefault(exuInput)
132    newExuInput.loadDependency match {
133      case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1)
134      case None =>
135    }
136    newExuInput
137  }
138
139  private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = {
140    val lastExuInput = WireDefault(exuInput)
141    val newExuInput = WireDefault(newInput)
142    newExuInput.elements.foreach { case (name, data) =>
143      if (lastExuInput.elements.contains(name)) {
144        data := lastExuInput.elements(name)
145      }
146    }
147    if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) {
148      newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest)
149    }
150    if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) {
151      newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
152    }
153    if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) {
154      newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get)
155    }
156    if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) {
157      newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
158    }
159    if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) {
160      newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get)
161    }
162    newExuInput
163  }
164
165  val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module(
166    new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc)
167  ))}
168  val deqBeforeDly = Wire(params.genIssueDecoupledBundle)
169
170  val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable)
171  val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable)
172  val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable)
173  val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable)
174  val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet)
175  val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet)
176  val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
177  val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
178  val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
179  val s0_enqValidVec = io.enq.map(_.valid)
180  val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
181  val s0_enqNotFlush = !io.flush.valid
182  val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits)))
183  val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady
184
185
186  val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool()))
187  val finalDeqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
188
189  val validVec = VecInit(entries.io.valid.asBools)
190  val canIssueVec = VecInit(entries.io.canIssue.asBools)
191  dontTouch(canIssueVec)
192  val deqFirstIssueVec = entries.io.isFirstIssue
193
194  val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources
195  val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources)))
196  val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency
197  val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency)))
198  // (entryIdx)(srcIdx)(exuIdx)
199  val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH
200  val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer
201
202  // (deqIdx)(srcIdx)(exuIdx)
203  val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
204  val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
205
206  val fuTypeVec = Wire(Vec(params.numEntries, FuType()))
207  val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))
208  val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
209  val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
210
211  //deq
212  val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W))))
213  val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W)))))
214  val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W)))))
215  val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W))))
216  val deqSelValidVec = Wire(Vec(params.numDeq, Bool()))
217  val deqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
218  val cancelDeqVec = Wire(Vec(params.numDeq, Bool()))
219
220  val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool())))
221  val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W))))
222  val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W)))
223
224  //trans
225  val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W))))
226  val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W))))
227  val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W))))
228  val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W))))
229  simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get))
230
231  /**
232    * Connection of [[entries]]
233    */
234  entries.io match { case entriesIO: EntriesIO =>
235    entriesIO.flush                                             := io.flush
236    entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) =>
237      enq.valid                                                 := s0_doEnqSelValidVec(enqIdx)
238      enq.bits.status.robIdx                                    := s0_enqBits(enqIdx).robIdx
239      enq.bits.status.fuType                                    := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType))
240      val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size)
241      for(j <- 0 until numLsrc) {
242        enq.bits.status.srcStatus(j).psrc                       := s0_enqBits(enqIdx).psrc(j)
243        enq.bits.status.srcStatus(j).srcType                    := s0_enqBits(enqIdx).srcType(j)
244        enq.bits.status.srcStatus(j).srcState                   := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel)
245        enq.bits.status.srcStatus(j).dataSources.value          := Mux(
246          SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U),
247          DataSource.zero,
248          Mux(SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)), DataSource.imm, DataSource.reg)
249        )
250        enq.bits.status.srcStatus(j).srcLoadDependency          := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x(x.getWidth - 2, 0) << 1))
251        if(params.hasIQWakeUp) {
252          enq.bits.status.srcStatus(j).srcTimer.get             := 0.U(3.W)
253          enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get     := 0.U.asTypeOf(ExuVec())
254        }
255      }
256      enq.bits.status.blocked                                   := false.B
257      enq.bits.status.issued                                    := false.B
258      enq.bits.status.firstIssue                                := false.B
259      enq.bits.status.issueTimer                                := "b10".U
260      enq.bits.status.deqPortIdx                                := 0.U
261      if (params.inIntSchd && params.AluCnt > 0) {
262        // dirty code for lui+addi(w) fusion
263        val isLuiAddiFusion = s0_enqBits(enqIdx).isLUI32
264        val luiImm = Cat(s0_enqBits(enqIdx).lsrc(1), s0_enqBits(enqIdx).lsrc(0), s0_enqBits(enqIdx).imm(ImmUnion.maxLen - 1, 0))
265        enq.bits.imm.foreach(_ := Mux(isLuiAddiFusion, ImmUnion.LUI32.toImm32(luiImm), s0_enqBits(enqIdx).imm))
266      }
267      else if (params.isLdAddrIQ || params.isHyAddrIQ) {
268        // dirty code for fused_lui_load
269        val isLuiLoadFusion = SrcType.isNotReg(s0_enqBits(enqIdx).srcType(0)) && FuType.isLoad(s0_enqBits(enqIdx).fuType)
270        enq.bits.imm.foreach(_ := Mux(isLuiLoadFusion, Imm_LUI_LOAD().getLuiImm(s0_enqBits(enqIdx)), s0_enqBits(enqIdx).imm))
271      }
272      else {
273        enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm)
274      }
275      enq.bits.payload                                          := s0_enqBits(enqIdx)
276    }
277    entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) =>
278      og0Resp                                                   := io.og0Resp(i)
279    }
280    entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) =>
281      og1Resp                                                   := io.og1Resp(i)
282    }
283    if (params.isLdAddrIQ || params.isHyAddrIQ) {
284      entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) =>
285        finalIssueResp                                          := io.finalIssueResp.get(i)
286      }
287      entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) =>
288        memAddrIssueResp                                        := io.memAddrIssueResp.get(i)
289      }
290    }
291    if (params.isVecLduIQ) {
292      entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) =>
293        resp                                                    := io.vecLoadIssueResp.get(i)
294      }
295    }
296    for(deqIdx <- 0 until params.numDeq) {
297      entriesIO.deqReady(deqIdx)                                := deqBeforeDly(deqIdx).ready
298      entriesIO.deqSelOH(deqIdx).valid                          := deqSelValidVec(deqIdx)
299      entriesIO.deqSelOH(deqIdx).bits                           := deqSelOHVec(deqIdx)
300      entriesIO.enqEntryOldestSel(deqIdx)                       := enqEntryOldestSel(deqIdx)
301      entriesIO.simpEntryOldestSel.foreach(_(deqIdx)            := simpEntryOldestSel.get(deqIdx))
302      entriesIO.compEntryOldestSel.foreach(_(deqIdx)            := compEntryOldestSel.get(deqIdx))
303      entriesIO.othersEntryOldestSel.foreach(_(deqIdx)          := othersEntryOldestSel(deqIdx))
304      entriesIO.subDeqRequest.foreach(_(deqIdx)                 := subDeqRequest.get)
305      entriesIO.subDeqSelOH.foreach(_(deqIdx)                   := subDeqSelOHVec.get(deqIdx))
306    }
307    entriesIO.wakeUpFromWB                                      := io.wakeupFromWB
308    entriesIO.wakeUpFromIQ                                      := io.wakeupFromIQ
309    entriesIO.vlIsZero                                          := io.vlIsZero
310    entriesIO.vlIsVlmax                                         := io.vlIsVlmax
311    entriesIO.og0Cancel                                         := io.og0Cancel
312    entriesIO.og1Cancel                                         := io.og1Cancel
313    entriesIO.ldCancel                                          := io.ldCancel
314    entriesIO.simpEntryDeqSelVec.foreach(_                      := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits)))
315    //output
316    fuTypeVec                                                   := entriesIO.fuType
317    deqEntryVec                                                 := entriesIO.deqEntry
318    cancelDeqVec                                                := entriesIO.cancelDeqVec
319    simpEntryEnqSelVec.foreach(_                                := entriesIO.simpEntryEnqSelVec.get)
320    compEntryEnqSelVec.foreach(_                                := entriesIO.compEntryEnqSelVec.get)
321    othersEntryEnqSelVec.foreach(_                              := entriesIO.othersEntryEnqSelVec.get)
322  }
323
324
325  s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready}
326
327  protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType =>
328    FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType))
329  ).reverse)
330
331  // if deq port can accept the uop
332  protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
333    Cat(fuTypeVec.map(fuType =>
334      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))
335    ).reverse)
336  }
337
338  protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
339    fuTypeVec.map(fuType =>
340      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
341  }
342
343  canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) =>
344    val mergeFuBusy = {
345      if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i))
346      else canIssueVec.asUInt
347    }
348    val mergeIntWbBusy = {
349      if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i))
350      else mergeFuBusy
351    }
352    val mergeVfWbBusy = {
353      if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i))
354      else mergeIntWbBusy
355    }
356    merge := mergeVfWbBusy
357  }
358
359  deqCanIssue.zipWithIndex.foreach { case (req, i) =>
360    req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt
361  }
362  dontTouch(fuTypeVec)
363  dontTouch(canIssueMergeAllBusy)
364  dontTouch(deqCanIssue)
365
366  if (params.numDeq == 2) {
367    require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different")
368  }
369
370  if (params.numDeq == 2 && params.deqFuSame) {
371    val subDeqPolicy = Module(new DeqPolicy())
372
373    enqEntryOldestSel := DontCare
374
375    if (params.isAllComp || params.isAllSimp) {
376      othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq,
377        enq = othersEntryEnqSelVec.get,
378        canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq)
379      )
380      othersEntryOldestSel(1) := DontCare
381
382      subDeqPolicy.io.request := subDeqRequest.get
383      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
384      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits)
385    }
386    else {
387      simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq)
388      simpAgeDetectRequest.get(1) := DontCare
389      simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt
390      if (params.numEnq == 2) {
391        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
392      }
393
394      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
395        enq = simpEntryEnqSelVec.get,
396        canIssue = simpAgeDetectRequest.get
397      )
398
399      compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp,
400        enq = compEntryEnqSelVec.get,
401        canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp)
402      )
403      compEntryOldestSel.get(1) := DontCare
404
405      othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid
406      othersEntryOldestSel(0).bits := Cat(
407        compEntryOldestSel.get(0).bits,
408        Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits,
409      )
410      othersEntryOldestSel(1) := DontCare
411
412      subDeqPolicy.io.request := Reverse(subDeqRequest.get)
413      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
414      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits))
415    }
416
417    subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W))
418
419    deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1)
420    deqSelValidVec(1) := subDeqSelValidVec.get(0)
421    deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid,
422                          Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)),
423                          subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0)
424    deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1)
425
426    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
427      selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready
428      selOH := deqOH
429    }
430  }
431  else {
432    enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq,
433      enq = VecInit(s0_doEnqSelValidVec),
434      canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0)))
435    )
436
437    if (params.isAllComp || params.isAllSimp) {
438      othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq,
439        enq = othersEntryEnqSelVec.get,
440        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq)))
441      )
442
443      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
444        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
445          selValid := false.B
446          selOH := 0.U.asTypeOf(selOH)
447        } else {
448          selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid
449          selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits)
450        }
451      }
452    }
453    else {
454      othersEntryOldestSel := DontCare
455
456      deqCanIssue.zipWithIndex.foreach { case (req, i) =>
457        simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq)
458      }
459      simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt
460      if (params.numEnq == 2) {
461        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
462      }
463
464      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
465        enq = simpEntryEnqSelVec.get,
466        canIssue = simpAgeDetectRequest.get
467      )
468
469      compEntryOldestSel.get := AgeDetector(numEntries = params.numComp,
470        enq = compEntryEnqSelVec.get,
471        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp)))
472      )
473
474      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
475        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
476          selValid := false.B
477          selOH := 0.U.asTypeOf(selOH)
478        } else {
479          selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid
480          selOH := Cat(
481            compEntryOldestSel.get(i).bits,
482            Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits,
483            Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits
484          )
485        }
486      }
487    }
488
489    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
490      selValid := deqValid && deqBeforeDly(i).ready
491      selOH := deqOH
492    }
493  }
494
495  val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle)))
496
497  toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) =>
498    deqResp.valid := finalDeqSelValidVec(i)
499    deqResp.bits.resp   := RespType.success
500    deqResp.bits.robIdx := DontCare
501    deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType
502    deqResp.bits.uopIdx.foreach(_ := DontCare)
503  }
504
505  //fuBusyTable
506  fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) =>
507    if(busyTableWrite.nonEmpty) {
508      val btwr = busyTableWrite.get
509      val btrd = busyTableRead.get
510      btwr.io.in.deqResp := toBusyTableDeqResp(i)
511      btwr.io.in.og0Resp := io.og0Resp(i)
512      btwr.io.in.og1Resp := io.og1Resp(i)
513      btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable
514      btrd.io.in.fuTypeRegVec := fuTypeVec
515      fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask
516    }
517    else {
518      fuBusyTableMask(i) := 0.U(params.numEntries.W)
519    }
520  }
521
522  //wbfuBusyTable write
523  intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
524    if(busyTableWrite.nonEmpty) {
525      val btwr = busyTableWrite.get
526      val bt = busyTable.get
527      val dq = deqResp.get
528      btwr.io.in.deqResp := toBusyTableDeqResp(i)
529      btwr.io.in.og0Resp := io.og0Resp(i)
530      btwr.io.in.og1Resp := io.og1Resp(i)
531      bt := btwr.io.out.fuBusyTable
532      dq := btwr.io.out.deqRespSet
533    }
534  }
535
536  vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
537    if (busyTableWrite.nonEmpty) {
538      val btwr = busyTableWrite.get
539      val bt = busyTable.get
540      val dq = deqResp.get
541      btwr.io.in.deqResp := toBusyTableDeqResp(i)
542      btwr.io.in.og0Resp := io.og0Resp(i)
543      btwr.io.in.og1Resp := io.og1Resp(i)
544      bt := btwr.io.out.fuBusyTable
545      dq := btwr.io.out.deqRespSet
546    }
547  }
548
549  //wbfuBusyTable read
550  intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
551    if(busyTableRead.nonEmpty) {
552      val btrd = busyTableRead.get
553      val bt = busyTable.get
554      btrd.io.in.fuBusyTable := bt
555      btrd.io.in.fuTypeRegVec := fuTypeVec
556      intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
557    }
558    else {
559      intWbBusyTableMask(i) := 0.U(params.numEntries.W)
560    }
561  }
562  vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
563    if (busyTableRead.nonEmpty) {
564      val btrd = busyTableRead.get
565      val bt = busyTable.get
566      btrd.io.in.fuBusyTable := bt
567      btrd.io.in.fuTypeRegVec := fuTypeVec
568      vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
569    }
570    else {
571      vfWbBusyTableMask(i) := 0.U(params.numEntries.W)
572    }
573  }
574
575  wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) =>
576    wakeUpQueueOption.foreach {
577      wakeUpQueue =>
578        val flush = Wire(new WakeupQueueFlush)
579        flush.redirect := io.flush
580        flush.ldCancel := io.ldCancel
581        flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp)
582        flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp)
583        wakeUpQueue.io.flush := flush
584        wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid
585        wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common
586        wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U)
587        wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType)
588    }
589  }
590
591  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
592    deq.valid                := finalDeqSelValidVec(i) && !cancelDeqVec(i)
593    deq.bits.addrOH          := finalDeqSelOHVec(i)
594    deq.bits.common.isFirstIssue := deqFirstIssueVec(i)
595    deq.bits.common.iqIdx    := OHToUInt(finalDeqSelOHVec(i))
596    deq.bits.common.fuType   := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt
597    deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType
598    deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen)
599    deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen)
600    deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen)
601    deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe)
602    deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest
603    deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx
604
605    require(deq.bits.common.dataSources.size <= finalDataSources(i).size)
606    deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source}
607    deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i))
608    deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i))
609    deq.bits.common.loadDependency.foreach(_ := finalLoadDependency(i))
610    deq.bits.common.src := DontCare
611    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
612
613    deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) =>
614      // psrc in status array can be pregIdx of IntRegFile or VfRegFile
615      rf.foreach(_.addr := psrc)
616      rf.foreach(_.srcType := srcType)
617    }
618    deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) =>
619      sink := source
620    }
621    deq.bits.immType := deqEntryVec(i).bits.payload.selImm
622    deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U)
623
624    deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo
625    deq.bits.common.perfDebugInfo.selectTime := GTimer()
626    deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U
627  }
628
629  private val deqShift = WireDefault(deqBeforeDly)
630  deqShift.zip(deqBeforeDly).foreach {
631    case (shifted, original) =>
632      original.ready := shifted.ready // this will not cause combinational loop
633      shifted.bits.common.loadDependency.foreach(
634        _ := original.bits.common.loadDependency.get.map(_ << 1)
635      )
636  }
637  io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) =>
638    NewPipelineConnect(
639      deq, deqDly, deqDly.valid,
640      false.B,
641      Option("Scheduler2DataPathPipe")
642    )
643  }
644  if(backendParams.debugEn) {
645    dontTouch(io.deqDelay)
646  }
647  io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) =>
648    if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) {
649      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
650      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i))
651      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
652      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
653    } else if (wakeUpQueues(i).nonEmpty) {
654      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
655      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits)
656      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
657      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
658    } else {
659      wakeup.valid := false.B
660      wakeup.bits := 0.U.asTypeOf(wakeup.bits)
661      wakeup.bits.is0Lat :=  0.U
662    }
663    if (wakeUpQueues(i).nonEmpty) {
664      wakeup.bits.rfWen  := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B)
665      wakeup.bits.fpWen  := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B)
666      wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B)
667    }
668
669    if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){
670      wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get
671    }
672    if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) {
673      wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get
674    }
675    if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) {
676      wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get
677    }
678    if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) {
679      wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get
680    }
681    if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) {
682      wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get
683    }
684  }
685
686  // Todo: better counter implementation
687  private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _)
688  private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq))
689  private val othersValidCnt = PopCount(validVec.drop(params.numEnq))
690  private val enqEntryValidCntDeq0 = PopCount(
691    validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b }
692  )
693  private val othersValidCntDeq0 = PopCount(
694    validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b }
695  )
696  private val enqEntryValidCntDeq1 = PopCount(
697    validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b }
698  )
699  private val othersValidCntDeq1 = PopCount(
700    validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b }
701  )
702  protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
703    io.enq.map(_.bits.fuType).map(fuType =>
704      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
705  }
706  protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b })
707  protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b })
708  io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0)
709  io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1)
710  io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _)
711  for (i <- 0 until params.numEnq) {
712    io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U
713  }
714  private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W)))
715  othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) =>
716    leftone := ~(1.U((params.numEntries - params.numEnq).W) << i)
717  }
718  private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _)
719  private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _)
720
721  io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid)
722  io.status.empty := !Cat(validVec).orR
723  io.status.full := othersCanotIn
724  io.status.validCnt := PopCount(validVec)
725
726  protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = {
727    Mux1H(fuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) })
728  }
729
730  // issue perf counter
731  // enq count
732  XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire)))
733  XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire)))
734  XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) }))
735  XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) }))
736  XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire))
737  XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire))
738  // valid count
739  XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1)
740  XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1)
741  XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1)
742  // only split when more than 1 func type
743  if (params.getFuCfgs.size > 0) {
744    for (t <- FuType.functionNameMap.keys) {
745      val fuName = FuType.functionNameMap(t)
746      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
747        XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1)
748      }
749    }
750  }
751  // ready instr count
752  private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2))
753  XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1)
754  // only split when more than 1 func type
755  if (params.getFuCfgs.size > 0) {
756    for (t <- FuType.functionNameMap.keys) {
757      val fuName = FuType.functionNameMap(t)
758      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
759        XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1)
760      }
761    }
762  }
763
764  // deq instr count
765  XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid)))
766  XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
767  XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid)))
768  XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
769
770  // deq instr data source count
771  XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq =>
772    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
773  }.reduce(_ +& _))
774  XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq =>
775    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
776  }.reduce(_ +& _))
777  XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq =>
778    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
779  }.reduce(_ +& _))
780  XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq =>
781    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
782  }.reduce(_ +& _))
783
784  XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq =>
785    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
786  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
787  XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq =>
788    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
789  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
790  XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq =>
791    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
792  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
793  XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq =>
794    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
795  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
796
797  // deq instr data source count for each futype
798  for (t <- FuType.functionNameMap.keys) {
799    val fuName = FuType.functionNameMap(t)
800    if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
801      XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq =>
802        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
803      }.reduce(_ +& _))
804      XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq =>
805        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
806      }.reduce(_ +& _))
807      XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq =>
808        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
809      }.reduce(_ +& _))
810      XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq =>
811        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
812      }.reduce(_ +& _))
813
814      XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
815        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
816      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
817      XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
818        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
819      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
820      XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
821        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
822      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
823      XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
824        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
825      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
826    }
827  }
828
829  // cancel instr count
830  if (params.hasIQWakeUp) {
831    val cancelVec: Vec[Bool] = entries.io.cancel.get
832    XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)))
833    XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1)
834    for (t <- FuType.functionNameMap.keys) {
835      val fuName = FuType.functionNameMap(t)
836      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
837        XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }))
838        XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1)
839      }
840    }
841  }
842}
843
844class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle {
845  val fastMatch = UInt(backendParams.LduCnt.W)
846  val fastImm = UInt(12.W)
847}
848
849class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO
850
851class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
852  extends IssueQueueImp(wrapper)
853{
854  io.suggestName("none")
855  override lazy val io = IO(new IssueQueueIntIO).suggestName("io")
856
857  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
858    deq.bits.common.pc.foreach(_ := DontCare)
859    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
860    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
861    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
862    deq.bits.common.predictInfo.foreach(x => {
863      x.target := DontCare
864      x.taken := deqEntryVec(i).bits.payload.pred_taken
865    })
866    // for std
867    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
868    // for i2f
869    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
870  }}
871}
872
873class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
874  extends IssueQueueImp(wrapper)
875{
876  s0_enqBits.foreach{ x =>
877    x.srcType(3) := SrcType.vp // v0: mask src
878    x.srcType(4) := SrcType.vp // vl&vtype
879  }
880  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
881    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
882    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
883    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
884    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
885  }}
886}
887
888class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle {
889  val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ)))
890
891  // TODO: is still needed?
892  val checkWait = new Bundle {
893    val stIssuePtr = Input(new SqPtr)
894    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
895  }
896  val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle))
897
898  // load wakeup
899  val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst())))
900
901  // vector
902  val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr))
903  val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr))
904}
905
906class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO {
907  val memIO = Some(new IssueQueueMemBundle)
908}
909
910class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
911  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
912
913  require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " +
914    s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
915  println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
916
917  io.suggestName("none")
918  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
919  private val memIO = io.memIO.get
920
921  memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed?
922
923  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
924    slowResp.valid       := memIO.feedbackIO(i).feedbackSlow.valid
925    slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
926    slowResp.bits.resp   := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
927    slowResp.bits.fuType := DontCare
928  }
929
930  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
931    fastResp.valid       := memIO.feedbackIO(i).feedbackFast.valid
932    fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx
933    fastResp.bits.resp   := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
934    fastResp.bits.fuType := DontCare
935  }
936
937  // load wakeup
938  val loadWakeUpIter = memIO.loadWakeUp.iterator
939  io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) =>
940    if (param.hasLoadExu) {
941      require(wakeUpQueues(i).isEmpty)
942      val uop = loadWakeUpIter.next()
943
944      wakeup.valid := GatedValidRegNext(uop.fire)
945      wakeup.bits.rfWen  := GatedValidRegNext(uop.bits.rfWen  && uop.fire)
946      wakeup.bits.fpWen  := GatedValidRegNext(uop.bits.fpWen  && uop.fire)
947      wakeup.bits.vecWen := GatedValidRegNext(uop.bits.vecWen && uop.fire)
948      wakeup.bits.pdest  := RegEnable(uop.bits.pdest, uop.fire)
949      wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only
950
951      wakeup.bits.rfWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.rfWen  && uop.fire)))
952      wakeup.bits.fpWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.fpWen  && uop.fire)))
953      wakeup.bits.vecWenCopy.foreach(_.foreach(_ := GatedValidRegNext(uop.bits.vecWen && uop.fire)))
954      wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire)))
955      wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only
956
957      wakeup.bits.is0Lat := 0.U
958    }
959  }
960  require(!loadWakeUpIter.hasNext)
961
962  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
963    deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit)
964    deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx)
965    deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit)
966    deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict)
967    deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid)
968    deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx
969    deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx
970    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
971    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
972  }
973}
974
975class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
976  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
977
978  require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ")
979  println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}")
980
981  io.suggestName("none")
982  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
983  private val memIO = io.memIO.get
984
985  require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports")
986
987  def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = {
988    val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j))))
989    val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j =>
990      (if (j < i) !valid(j) || compareVec(i)(j)
991      else if (j == i) valid(i)
992      else !valid(j) || !compareVec(j)(i))
993    )).andR))
994    resultOnehot
995  }
996
997  s0_enqBits.foreach{ x =>
998    x.srcType(3) := SrcType.vp // v0: mask src
999    x.srcType(4) := SrcType.vp // vl&vtype
1000  }
1001
1002  for (i <- entries.io.enq.indices) {
1003    entries.io.enq(i).bits.status match { case enqData =>
1004      enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx
1005      enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx
1006      // MemAddrIQ also handle vector insts
1007      enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem
1008      enqData.blocked          := false.B
1009    }
1010  }
1011
1012  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
1013    slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
1014    slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
1015    slowResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
1016    slowResp.bits.fuType           := DontCare
1017    slowResp.bits.uopIdx.get       := memIO.feedbackIO(i).feedbackSlow.bits.uopIdx.get
1018  }
1019
1020  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
1021    fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
1022    fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
1023    fastResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
1024    fastResp.bits.fuType           := DontCare
1025    fastResp.bits.uopIdx.get       := memIO.feedbackIO(i).feedbackFast.bits.uopIdx.get
1026  }
1027
1028  entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get
1029  entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get
1030
1031  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
1032    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx)
1033    deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx)
1034    deq.bits.common.numLsElem.get := deqEntryVec(i).bits.status.vecMem.get.numLsElem
1035    deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem)
1036    if (params.isVecLduIQ) {
1037      deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr
1038      deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset
1039    }
1040    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
1041    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
1042    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
1043    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
1044  }
1045
1046  io.vecLoadIssueResp.foreach(dontTouch(_))
1047}
1048