1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne} 8import utils._ 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.issue.EntryBundles._ 12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 13import xiangshan.backend.datapath.DataConfig._ 14import xiangshan.backend.datapath.DataSource 15import xiangshan.backend.fu.{FuConfig, FuType} 16import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 17import xiangshan.backend.rob.RobPtr 18import xiangshan.backend.datapath.NewPipelineConnect 19import xiangshan.backend.fu.vector.Bundles.VSew 20 21class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 22 override def shouldBeInlined: Boolean = false 23 24 implicit val iqParams = params 25 lazy val module: IssueQueueImp = iqParams.schdType match { 26 case IntScheduler() => new IssueQueueIntImp(this) 27 case FpScheduler() => new IssueQueueFpImp(this) 28 case VfScheduler() => new IssueQueueVfImp(this) 29 case MemScheduler() => 30 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 31 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 32 else new IssueQueueIntImp(this) 33 case _ => null 34 } 35} 36 37class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 38 val empty = Output(Bool()) 39 val full = Output(Bool()) 40 val validCnt = Output(UInt(log2Ceil(numEntries).W)) 41 val leftVec = Output(Vec(numEnq + 1, Bool())) 42} 43 44class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 45 46class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 47 // Inputs 48 val flush = Flipped(ValidIO(new Redirect)) 49 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 50 51 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 52 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 53 val og2Resp = OptionWrapper(params.inVfSchd, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 54 val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 55 val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 56 val vecLoadIssueResp = OptionWrapper(params.VlduCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 57 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle()) 58 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle()) 59 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 60 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 61 val vlIsZero = Input(Bool()) 62 val vlIsVlmax = Input(Bool()) 63 val og0Cancel = Input(ExuOH(backendParams.numExu)) 64 val og1Cancel = Input(ExuOH(backendParams.numExu)) 65 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 66 67 // Outputs 68 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 69 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 70 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 71 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 72 73 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 74 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 75} 76 77class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 78 extends LazyModuleImp(wrapper) 79 with HasXSParameter { 80 81 override def desiredName: String = s"${params.getIQName}" 82 83 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 84 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 85 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 86 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 87 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 88 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 89 90 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 91 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 92 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 93 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 94 95 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 96 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 97 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 98 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 99 val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap) 100 101 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}") 102 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 103 lazy val io = IO(new IssueQueueIO()) 104 105 // Modules 106 val entries = Module(new Entries) 107 val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) } 108 val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) } 109 val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 110 val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) } 111 val fpWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.fpLatencyCertain, Module(new FuBusyTableWrite(x.fpFuLatencyMap))) } 112 val fpWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.fpLatencyCertain, Module(new FuBusyTableRead(x.fpFuLatencyMap))) } 113 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 114 val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 115 116 class WakeupQueueFlush extends Bundle { 117 val redirect = ValidIO(new Redirect) 118 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 119 val og0Fail = Output(Bool()) 120 val og1Fail = Output(Bool()) 121 } 122 123 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 124 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 125 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 126 val ogFailFlush = stage match { 127 case 1 => flush.og0Fail 128 case 2 => flush.og1Fail 129 case _ => false.B 130 } 131 redirectFlush || loadDependencyFlush || ogFailFlush 132 } 133 134 private def modificationFunc(exuInput: ExuInput): ExuInput = { 135 val newExuInput = WireDefault(exuInput) 136 newExuInput.loadDependency match { 137 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 138 case None => 139 } 140 newExuInput 141 } 142 143 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 144 val lastExuInput = WireDefault(exuInput) 145 val newExuInput = WireDefault(newInput) 146 newExuInput.elements.foreach { case (name, data) => 147 if (lastExuInput.elements.contains(name)) { 148 data := lastExuInput.elements(name) 149 } 150 } 151 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 152 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 153 } 154 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 155 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 156 } 157 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 158 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 159 } 160 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 161 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 162 } 163 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 164 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 165 } 166 newExuInput 167 } 168 169 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module( 170 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 171 ))} 172 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 173 174 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 175 val fpWbBusyTableIn = io.wbBusyTableRead.map(_.fpWbBusyTable) 176 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 177 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 178 val fpWbBusyTableOut = io.wbBusyTableWrite.map(_.fpWbBusyTable) 179 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 180 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 181 val fpDeqRespSetOut = io.wbBusyTableWrite.map(_.fpDeqRespSet) 182 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 183 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 184 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 185 val fpWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 186 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 187 val s0_enqValidVec = io.enq.map(_.valid) 188 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 189 val s0_enqNotFlush = !io.flush.valid 190 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 191 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 192 193 194 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 195 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 196 197 val validVec = VecInit(entries.io.valid.asBools) 198 val canIssueVec = VecInit(entries.io.canIssue.asBools) 199 dontTouch(canIssueVec) 200 val deqFirstIssueVec = entries.io.isFirstIssue 201 202 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 203 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 204 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 205 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 206 // (entryIdx)(srcIdx)(exuIdx) 207 val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH 208 // (deqIdx)(srcIdx)(exuIdx) 209 val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 210 211 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 212 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 213 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 214 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 215 216 //deq 217 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 218 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 219 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 220 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 221 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 222 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 223 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 224 225 val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool()))) 226 val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 227 val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W))) 228 229 //trans 230 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 231 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 232 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 233 val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 234 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 235 236 // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle 237 // as vf exu's min latency is 1, we do not need consider og0cancel 238 val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ)) 239 wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) => 240 if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) { 241 val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel) 242 w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w))) 243 w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) } 244 } else { 245 w := w_src 246 } 247 } 248 249 /** 250 * Connection of [[entries]] 251 */ 252 entries.io match { case entriesIO: EntriesIO => 253 entriesIO.flush := io.flush 254 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 255 enq.valid := s0_doEnqSelValidVec(enqIdx) 256 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 257 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 258 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 259 for(j <- 0 until numLsrc) { 260 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 261 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 262 enq.bits.status.srcStatus(j).srcState := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel) 263 enq.bits.status.srcStatus(j).dataSources.value := Mux( 264 SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 265 DataSource.zero, 266 Mux(SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)), DataSource.imm, DataSource.reg) 267 ) 268 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x << 1)) 269 if(params.hasIQWakeUp) { 270 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 271 } 272 } 273 enq.bits.status.blocked := false.B 274 enq.bits.status.issued := false.B 275 enq.bits.status.firstIssue := false.B 276 enq.bits.status.issueTimer := "b11".U 277 enq.bits.status.deqPortIdx := 0.U 278 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 279 enq.bits.payload := s0_enqBits(enqIdx) 280 } 281 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 282 og0Resp := io.og0Resp(i) 283 } 284 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 285 og1Resp := io.og1Resp(i) 286 } 287 if (params.inVfSchd) { 288 entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) => 289 og2Resp := io.og2Resp.get(i) 290 } 291 } 292 if (params.isLdAddrIQ || params.isHyAddrIQ) { 293 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 294 finalIssueResp := io.finalIssueResp.get(i) 295 } 296 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 297 memAddrIssueResp := io.memAddrIssueResp.get(i) 298 } 299 } 300 if (params.isVecLduIQ) { 301 entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) => 302 resp := io.vecLoadIssueResp.get(i) 303 } 304 } 305 for(deqIdx <- 0 until params.numDeq) { 306 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 307 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 308 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 309 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 310 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 311 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 312 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 313 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 314 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 315 } 316 entriesIO.wakeUpFromWB := io.wakeupFromWB 317 entriesIO.wakeUpFromIQ := wakeupFromIQ 318 entriesIO.vlIsZero := io.vlIsZero 319 entriesIO.vlIsVlmax := io.vlIsVlmax 320 entriesIO.og0Cancel := io.og0Cancel 321 entriesIO.og1Cancel := io.og1Cancel 322 entriesIO.ldCancel := io.ldCancel 323 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 324 //output 325 fuTypeVec := entriesIO.fuType 326 deqEntryVec := entriesIO.deqEntry 327 cancelDeqVec := entriesIO.cancelDeqVec 328 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 329 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 330 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 331 } 332 333 334 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 335 336 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 337 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 338 ).reverse) 339 340 // if deq port can accept the uop 341 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 342 Cat(fuTypeVec.map(fuType => 343 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 344 ).reverse) 345 } 346 347 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 348 fuTypeVec.map(fuType => 349 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 350 } 351 352 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 353 val mergeFuBusy = { 354 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 355 else canIssueVec.asUInt 356 } 357 val mergeIntWbBusy = { 358 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 359 else mergeFuBusy 360 } 361 val mergefpWbBusy = { 362 if (fpWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~fpWbBusyTableMask(i)) 363 else mergeIntWbBusy 364 } 365 val mergeVfWbBusy = { 366 if (vfWbBusyTableRead(i).nonEmpty) mergefpWbBusy & (~vfWbBusyTableMask(i)) 367 else mergefpWbBusy 368 } 369 merge := mergeVfWbBusy 370 } 371 372 deqCanIssue.zipWithIndex.foreach { case (req, i) => 373 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 374 } 375 dontTouch(fuTypeVec) 376 dontTouch(canIssueMergeAllBusy) 377 dontTouch(deqCanIssue) 378 379 if (params.numDeq == 2) { 380 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 381 } 382 383 if (params.numDeq == 2 && params.deqFuSame) { 384 val subDeqPolicy = Module(new DeqPolicy()) 385 386 enqEntryOldestSel := DontCare 387 388 if (params.isAllComp || params.isAllSimp) { 389 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 390 enq = othersEntryEnqSelVec.get, 391 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 392 ) 393 othersEntryOldestSel(1) := DontCare 394 395 subDeqPolicy.io.request := subDeqRequest.get 396 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 397 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 398 } 399 else { 400 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 401 simpAgeDetectRequest.get(1) := DontCare 402 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 403 if (params.numEnq == 2) { 404 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 405 } 406 407 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 408 enq = simpEntryEnqSelVec.get, 409 canIssue = simpAgeDetectRequest.get 410 ) 411 412 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 413 enq = compEntryEnqSelVec.get, 414 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 415 ) 416 compEntryOldestSel.get(1) := DontCare 417 418 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 419 othersEntryOldestSel(0).bits := Cat( 420 compEntryOldestSel.get(0).bits, 421 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 422 ) 423 othersEntryOldestSel(1) := DontCare 424 425 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 426 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 427 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 428 } 429 430 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 431 432 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 433 deqSelValidVec(1) := subDeqSelValidVec.get(0) 434 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 435 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 436 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 437 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 438 439 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 440 selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready 441 selOH := deqOH 442 } 443 } 444 else { 445 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 446 enq = VecInit(s0_doEnqSelValidVec), 447 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 448 ) 449 450 if (params.isAllComp || params.isAllSimp) { 451 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 452 enq = othersEntryEnqSelVec.get, 453 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 454 ) 455 456 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 457 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 458 selValid := false.B 459 selOH := 0.U.asTypeOf(selOH) 460 } else { 461 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 462 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 463 } 464 } 465 } 466 else { 467 othersEntryOldestSel := DontCare 468 469 deqCanIssue.zipWithIndex.foreach { case (req, i) => 470 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 471 } 472 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 473 if (params.numEnq == 2) { 474 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 475 } 476 477 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 478 enq = simpEntryEnqSelVec.get, 479 canIssue = simpAgeDetectRequest.get 480 ) 481 482 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 483 enq = compEntryEnqSelVec.get, 484 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 485 ) 486 487 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 488 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 489 selValid := false.B 490 selOH := 0.U.asTypeOf(selOH) 491 } else { 492 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 493 selOH := Cat( 494 compEntryOldestSel.get(i).bits, 495 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 496 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 497 ) 498 } 499 } 500 } 501 502 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 503 selValid := deqValid && deqBeforeDly(i).ready 504 selOH := deqOH 505 } 506 } 507 508 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 509 510 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 511 deqResp.valid := finalDeqSelValidVec(i) 512 deqResp.bits.resp := RespType.success 513 deqResp.bits.robIdx := DontCare 514 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 515 deqResp.bits.uopIdx.foreach(_ := DontCare) 516 } 517 518 //fuBusyTable 519 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 520 if(busyTableWrite.nonEmpty) { 521 val btwr = busyTableWrite.get 522 val btrd = busyTableRead.get 523 btwr.io.in.deqResp := toBusyTableDeqResp(i) 524 btwr.io.in.og0Resp := io.og0Resp(i) 525 btwr.io.in.og1Resp := io.og1Resp(i) 526 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 527 btrd.io.in.fuTypeRegVec := fuTypeVec 528 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 529 } 530 else { 531 fuBusyTableMask(i) := 0.U(params.numEntries.W) 532 } 533 } 534 535 //wbfuBusyTable write 536 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 537 if(busyTableWrite.nonEmpty) { 538 val btwr = busyTableWrite.get 539 val bt = busyTable.get 540 val dq = deqResp.get 541 btwr.io.in.deqResp := toBusyTableDeqResp(i) 542 btwr.io.in.og0Resp := io.og0Resp(i) 543 btwr.io.in.og1Resp := io.og1Resp(i) 544 bt := btwr.io.out.fuBusyTable 545 dq := btwr.io.out.deqRespSet 546 } 547 } 548 549 fpWbBusyTableWrite.zip(fpWbBusyTableOut).zip(fpDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 550 if (busyTableWrite.nonEmpty) { 551 val btwr = busyTableWrite.get 552 val bt = busyTable.get 553 val dq = deqResp.get 554 btwr.io.in.deqResp := toBusyTableDeqResp(i) 555 btwr.io.in.og0Resp := io.og0Resp(i) 556 btwr.io.in.og1Resp := io.og1Resp(i) 557 bt := btwr.io.out.fuBusyTable 558 dq := btwr.io.out.deqRespSet 559 } 560 } 561 562 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 563 if (busyTableWrite.nonEmpty) { 564 val btwr = busyTableWrite.get 565 val bt = busyTable.get 566 val dq = deqResp.get 567 btwr.io.in.deqResp := toBusyTableDeqResp(i) 568 btwr.io.in.og0Resp := io.og0Resp(i) 569 btwr.io.in.og1Resp := io.og1Resp(i) 570 bt := btwr.io.out.fuBusyTable 571 dq := btwr.io.out.deqRespSet 572 } 573 } 574 575 //wbfuBusyTable read 576 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 577 if(busyTableRead.nonEmpty) { 578 val btrd = busyTableRead.get 579 val bt = busyTable.get 580 btrd.io.in.fuBusyTable := bt 581 btrd.io.in.fuTypeRegVec := fuTypeVec 582 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 583 } 584 else { 585 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 586 } 587 } 588 fpWbBusyTableRead.zip(fpWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 589 if (busyTableRead.nonEmpty) { 590 val btrd = busyTableRead.get 591 val bt = busyTable.get 592 btrd.io.in.fuBusyTable := bt 593 btrd.io.in.fuTypeRegVec := fuTypeVec 594 fpWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 595 } 596 else { 597 fpWbBusyTableMask(i) := 0.U(params.numEntries.W) 598 } 599 } 600 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 601 if (busyTableRead.nonEmpty) { 602 val btrd = busyTableRead.get 603 val bt = busyTable.get 604 btrd.io.in.fuBusyTable := bt 605 btrd.io.in.fuTypeRegVec := fuTypeVec 606 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 607 } 608 else { 609 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 610 } 611 } 612 613 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 614 wakeUpQueueOption.foreach { 615 wakeUpQueue => 616 val flush = Wire(new WakeupQueueFlush) 617 flush.redirect := io.flush 618 flush.ldCancel := io.ldCancel 619 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 620 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 621 wakeUpQueue.io.flush := flush 622 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 623 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 624 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 625 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 626 } 627 } 628 629 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 630 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 631 deq.bits.addrOH := finalDeqSelOHVec(i) 632 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 633 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 634 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 635 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 636 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 637 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 638 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 639 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 640 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 641 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 642 643 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 644 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 645 deq.bits.common.l1ExuOH.foreach(_.zip(finalWakeUpL1ExuOH.get(i)).foreach { case (sink, source) => sink := source}) 646 deq.bits.common.srcTimer.foreach(_ := DontCare) 647 deq.bits.common.loadDependency.foreach(_.zip(finalLoadDependency(i)).foreach { case (sink, source) => sink := source}) 648 deq.bits.common.src := DontCare 649 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 650 651 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 652 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 653 rf.foreach(_.addr := psrc) 654 rf.foreach(_.srcType := srcType) 655 } 656 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 657 sink := source 658 } 659 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 660 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 661 662 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 663 deq.bits.common.perfDebugInfo.selectTime := GTimer() 664 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 665 } 666 667 io.deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) => 668 NewPipelineConnect( 669 deq, deqDly, deqDly.valid, 670 false.B, 671 Option("Scheduler2DataPathPipe") 672 ) 673 } 674 if(backendParams.debugEn) { 675 dontTouch(io.deqDelay) 676 } 677 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 678 if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) { 679 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 680 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i)) 681 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 682 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 683 } else if (wakeUpQueues(i).nonEmpty) { 684 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 685 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 686 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 687 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 688 } else { 689 wakeup.valid := false.B 690 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 691 wakeup.bits.is0Lat := 0.U 692 } 693 if (wakeUpQueues(i).nonEmpty) { 694 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 695 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 696 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 697 } 698 699 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 700 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 701 } 702 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 703 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 704 } 705 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 706 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 707 } 708 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 709 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 710 } 711 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 712 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 713 } 714 } 715 716 // Todo: better counter implementation 717 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 718 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 719 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 720 private val enqEntryValidCntDeq0 = PopCount( 721 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 722 ) 723 private val othersValidCntDeq0 = PopCount( 724 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 725 ) 726 private val enqEntryValidCntDeq1 = PopCount( 727 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 728 ) 729 private val othersValidCntDeq1 = PopCount( 730 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 731 ) 732 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 733 io.enq.map(_.bits.fuType).map(fuType => 734 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 735 } 736 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 737 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 738 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 739 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 740 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 741 for (i <- 0 until params.numEnq) { 742 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 743 } 744 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 745 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 746 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 747 } 748 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 749 private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 750 751 io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid) 752 io.status.empty := !Cat(validVec).orR 753 io.status.full := othersCanotIn 754 io.status.validCnt := PopCount(validVec) 755 756 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 757 Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 758 } 759 760 // issue perf counter 761 // enq count 762 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 763 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 764 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 765 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 766 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 767 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 768 // valid count 769 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 770 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 771 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 772 // only split when more than 1 func type 773 if (params.getFuCfgs.size > 0) { 774 for (t <- FuType.functionNameMap.keys) { 775 val fuName = FuType.functionNameMap(t) 776 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 777 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 778 } 779 } 780 } 781 // ready instr count 782 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 783 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 784 // only split when more than 1 func type 785 if (params.getFuCfgs.size > 0) { 786 for (t <- FuType.functionNameMap.keys) { 787 val fuName = FuType.functionNameMap(t) 788 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 789 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 790 } 791 } 792 } 793 794 // deq instr count 795 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 796 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 797 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 798 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 799 800 // deq instr data source count 801 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 802 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 803 }.reduce(_ +& _)) 804 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 805 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 806 }.reduce(_ +& _)) 807 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 808 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 809 }.reduce(_ +& _)) 810 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 811 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 812 }.reduce(_ +& _)) 813 814 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 815 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 816 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 817 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 818 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 819 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 820 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 821 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 822 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 823 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 824 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 825 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 826 827 // deq instr data source count for each futype 828 for (t <- FuType.functionNameMap.keys) { 829 val fuName = FuType.functionNameMap(t) 830 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 831 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 832 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 833 }.reduce(_ +& _)) 834 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 835 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 836 }.reduce(_ +& _)) 837 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 838 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 839 }.reduce(_ +& _)) 840 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 841 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 842 }.reduce(_ +& _)) 843 844 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 845 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 846 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 847 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 848 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 849 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 850 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 851 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 852 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 853 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 854 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 855 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 856 } 857 } 858} 859 860class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 861 val fastMatch = UInt(backendParams.LduCnt.W) 862 val fastImm = UInt(12.W) 863} 864 865class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 866 867class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 868 extends IssueQueueImp(wrapper) 869{ 870 io.suggestName("none") 871 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 872 873 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 874 deq.bits.common.pc.foreach(_ := DontCare) 875 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 876 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 877 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 878 deq.bits.common.predictInfo.foreach(x => { 879 x.target := DontCare 880 x.taken := deqEntryVec(i).bits.payload.pred_taken 881 }) 882 // for std 883 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 884 // for i2f 885 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 886 }} 887} 888 889class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 890 extends IssueQueueImp(wrapper) 891{ 892 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 893 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 894 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 895 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 896 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 897 }} 898} 899 900class IssueQueueFpImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 901 extends IssueQueueImp(wrapper) 902{ 903 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 904 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 905 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 906 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 907 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 908 }} 909} 910 911class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 912 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ))) 913 914 // TODO: is still needed? 915 val checkWait = new Bundle { 916 val stIssuePtr = Input(new SqPtr) 917 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 918 } 919 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 920 921 // load wakeup 922 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 923 924 // vector 925 val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr)) 926 val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr)) 927} 928 929class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 930 val memIO = Some(new IssueQueueMemBundle) 931} 932 933class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 934 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 935 936 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 937 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 938 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 939 940 io.suggestName("none") 941 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 942 private val memIO = io.memIO.get 943 944 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 945 946 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 947 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 948 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 949 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 950 slowResp.bits.fuType := DontCare 951 } 952 953 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 954 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 955 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 956 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 957 fastResp.bits.fuType := DontCare 958 } 959 960 // load wakeup 961 val loadWakeUpIter = memIO.loadWakeUp.iterator 962 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 963 if (param.hasLoadExu) { 964 require(wakeUpQueues(i).isEmpty) 965 val uop = loadWakeUpIter.next() 966 967 wakeup.valid := GatedValidRegNext(uop.fire) 968 wakeup.bits.rfWen := GatedValidRegNext(uop.bits.rfWen && uop.fire) 969 wakeup.bits.fpWen := GatedValidRegNext(uop.bits.fpWen && uop.fire) 970 wakeup.bits.vecWen := GatedValidRegNext(uop.bits.vecWen && uop.fire) 971 wakeup.bits.pdest := RegEnable(uop.bits.pdest, uop.fire) 972 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 973 974 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.rfWen && uop.fire))) 975 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.fpWen && uop.fire))) 976 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := GatedValidRegNext(uop.bits.vecWen && uop.fire))) 977 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire))) 978 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 979 980 wakeup.bits.is0Lat := 0.U 981 } 982 } 983 require(!loadWakeUpIter.hasNext) 984 985 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 986 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 987 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 988 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 989 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 990 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 991 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 992 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 993 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 994 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 995 } 996} 997 998class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 999 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1000 1001 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 1002 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 1003 1004 io.suggestName("none") 1005 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1006 private val memIO = io.memIO.get 1007 1008 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 1009 1010 for (i <- entries.io.enq.indices) { 1011 entries.io.enq(i).bits.status match { case enqData => 1012 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 1013 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 1014 // MemAddrIQ also handle vector insts 1015 enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem 1016 enqData.blocked := false.B 1017 } 1018 } 1019 1020 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1021 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1022 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1023 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1024 slowResp.bits.fuType := DontCare 1025 slowResp.bits.uopIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.uopIdx.get 1026 } 1027 1028 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1029 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1030 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1031 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1032 fastResp.bits.fuType := DontCare 1033 fastResp.bits.uopIdx.get := memIO.feedbackIO(i).feedbackFast.bits.uopIdx.get 1034 } 1035 1036 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1037 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1038 1039 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1040 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1041 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1042 deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem) 1043 if (params.isVecLduIQ) { 1044 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1045 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1046 } 1047 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1048 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1049 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1050 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1051 } 1052 1053 io.vecLoadIssueResp.foreach(dontTouch(_)) 1054} 1055